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Journal of Signal Processing Systems

, Volume 75, Issue 1, pp 39–46 | Cite as

Area Efficient Sequential Decimal Fixed-point Multiplier

  • Liu Han
  • Amir Kaivani
  • Seok-Bum KoEmail author
Article
  • 300 Downloads

Abstract

In this paper, a new architecture is proposed to reduce the area cost and power consumption of the decimal fixed-point multiplier. In the proposed sequential architecture, the partial product generation and selection cycles are reduced to one. Moreover, the elaborately selected easy multiples reduce the hardware requirement of the partial products selector. Subsequently, two partial products are accumulated with the iteration result in a redundant decimal format by a multi-operand redundant adder. The lower-significant half digits of the final product are iteratively converted in every cycle. On the other hand, the higher-significant half digits are converted by a carry-propagation adder in two extra cycles. After all, the area of the whole architecture is reduced significantly by not only the simpler partial product generation and accumulation architecture, but also the less registers. The synthesized result shows that the proposed sequential multiplier has a lower area cost and reasonable computation latency.

Keywords

Sequential multiplier Decimal arithmetic Redundant number system Area efficiency 

Notes

Acknowledgments

The authors would like to acknowledge the anonymous reviewers involved in the review of this manuscript. This project issupported by the Electrical and Computer Engineering department in University of Saskatchewan and the Natural Science andEngineering Research Council (NSERC) of Canada.

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Copyright information

© Springer Science+Business Media New York 2013

Authors and Affiliations

  1. 1.Department of Electrical and Computer EngineeringUniversity of SaskatchewanSaskatoonCanada

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