Area Efficient Sequential Decimal Fixed-point Multiplier
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In this paper, a new architecture is proposed to reduce the area cost and power consumption of the decimal fixed-point multiplier. In the proposed sequential architecture, the partial product generation and selection cycles are reduced to one. Moreover, the elaborately selected easy multiples reduce the hardware requirement of the partial products selector. Subsequently, two partial products are accumulated with the iteration result in a redundant decimal format by a multi-operand redundant adder. The lower-significant half digits of the final product are iteratively converted in every cycle. On the other hand, the higher-significant half digits are converted by a carry-propagation adder in two extra cycles. After all, the area of the whole architecture is reduced significantly by not only the simpler partial product generation and accumulation architecture, but also the less registers. The synthesized result shows that the proposed sequential multiplier has a lower area cost and reasonable computation latency.
KeywordsSequential multiplier Decimal arithmetic Redundant number system Area efficiency
The authors would like to acknowledge the anonymous reviewers involved in the review of this manuscript. This project issupported by the Electrical and Computer Engineering department in University of Saskatchewan and the Natural Science andEngineering Research Council (NSERC) of Canada.
- 1.IEEE Standard for Floating-Point Arithmetic. IEEE working group of the microprocesser standards subcommittee (2008).Google Scholar
- 2.Cowlishaw, M. F. (2003). Decimal floating-point algorism for computers. In Proc. of the 16th IEEE symposium on computer arithmetic.Google Scholar
- 5.Wang, L.-K. et al. (2007). Benchmarks and performance analysis of decimal floating-point applications. 25th International Conference on Computer Design (ICCD) (pp. 164–170).Google Scholar
- 8.Carlough, S., Collura, A., Mueller, S., Kroener, M. (2011). The IBM zEnterprise-196 decimal floating-point accelerator. 20th IEEE symposium on computer arithmetic.Google Scholar
- 11.Han, L., & Ko, S. (2013). High speed parallel decimal multiplication with redundant internal encodings. IEEE Transactions on Computers, 62(5), 956–968.Google Scholar
- 12.Cowlishaw, M. (2009). Decimal library performance. Version 1.12.Google Scholar
- 14.STMicroelectronics, 90nm CMOS Design Platform (2007).Google Scholar
- 15.Erle, M.A., & Schulte, M.J. (2003). Decimal multiplication via carry save addition. In Proc. IEEE Int. Conf. Application-Specific Systems, Architectures, Processors (pp. 337–347). Google Scholar
- 16.Kenney, R.D., Schulte M.J., Erle M. A. (2004) A high-frequency decimal multiplier. In Proc. IEEE int. conf. comput. des.: VLSI in comput. and processors (pp. 26–29). Google Scholar
- 17.Erle, M.A., Schwarz, E.M., Schulte, M.J. (2005). Decimal multiplication with efficient partial product generation. In Proc. 17th IEEE symp. on computer arithmetic (pp. 21–28).Google Scholar
- 18.Svoboda A. (1969) Decimal adder with signed digit arithmetic. IEEE Transaction on Computers, C, 212–215.Google Scholar