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Journal of Signal Processing Systems

, Volume 75, Issue 1, pp 85–92 | Cite as

Distributed Arithmetic based Split-Radix FFT

  • Sunil P. Joshi
  • Roy PailyEmail author
Article

Abstract

In this paper we have designed a Split-radix type FFT unit without using multipliers. All the complex multiplications required for this type of FFT are implemented using Distributed Arithmetic (DA) technique. A method is incorporated to overcome the result overflow problem introduced by DA method. Proposed FFT architecture is implemented in 180 nm CMOS technology at a supply voltage of 1.8 V.

Keywords

Fast fourier transforms (FFT) Split radix FFT (SRFFT) Distributed arithmetic (DA) ASIC implementation 

Notes

Acknowledgments

This work is carried out using the Synopsys and the Cadence tools provided by the SMDP II project at IIT Guwahati.

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Copyright information

© Springer Science+Business Media New York 2013

Authors and Affiliations

  1. 1.EEE DepartmentIIT GuwahatiGuwahatiIndia

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