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Optimized Hardware Implementation for Forward Quantization of H.264/AVC

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Abstract

An efficient implementation for the computation of the forward quantization of H.264/AVC is presented. It uses a modified reformulation of quantization expressions, in full compliance with the standard, combined with an adaptive truncated Booth multiplier to reduce hardware complexity. The JM reference software’s C code has been rewritten to analyze the effect of the proposed approach. Simulations carried out on several typical video sequences with different texture characteristics demonstrate the validity of this approach with an improvement in the PSNR at low QP, between a maximum of +0.8 dB and a minimum of 0.3 dB, with a slight increment in the bit-rate of about 0.8 %. However, this improvement is smoothed for typical values of QP and only an insignificant difference is found with respect to the JM results. The proposed architecture synthesized in the AMS 0.35μm technology, which is suitable for VLSI implementation, reduces the area by 26 %, the power by 32 % and the critical path delay by 21 % in comparison with a classic implementation.

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References

  1. Wiegand, T., Sullivan, G. J., Bjøntegaard, G., & Luthra, A. (2003). Overview of the H.264/AVC video coding standard. IEEE Transactions on Circuits and Systems for Video Technology, 13, 560–576.

    Article  Google Scholar 

  2. Richardson I. (2003). H.264 and MPEG-4 video compression. Wiley.

  3. [Online] Free on-line software available in http://iphome.hhi.de/suehring/tml/.

  4. Malvar, H., Hallapuro, A., Karczewicz, M., & Kerofsky, L. (2003). Low complexity transform and quantization in H.264/AVC. IEEE Transactions on Circuits and Systems for Video Technology, 13, 598–603.

    Article  Google Scholar 

  5. Kordasiewicz, R. C., & Shirani, S. (2004). Hardware implementation of the optimized transform and quantization blocks of H.264. 2004 Canadian Conference on Electrical and Computer Engineering, 2(2–5), 943–946.

    Google Scholar 

  6. Kordasiewicz, R.C., & Shirani S. (2005). ASIC and FPGA implementations of H.264 DCT and quantization blocks. Hardware implementation of the optimized transform and quantization blocks of H.264. IEEE International Conference on Image Processing 2005, ICIP 2005, pp. 1020–1023.

  7. Tasdizen, O., & Hamzaoglu I. (2005). A high performance and low cost hardware architecture for H.264 transform and quantization algorithms, 13th European Signal Processing Conference.

  8. Jou, S.J., & Wang H. H. (2000). Fixed-width multiplier for DSP application. Proceedings 2000 International Conference Computer Design (ICCD), Austin, TX, pp. 318–322.

  9. Zhang Y., Jiang G., Yi W., Yu M., Li F., Jiang, Z., Liu, W. (2006). An improved design of quantization for H.264 video coding standard, 8th International Conference on Signal Processing, vol. 2, pp. 201–204.

  10. Michael, M.N., & Hsu, K.W. (2008). A low-power design of quantization for H.264 video coding standard. IEEE International SOC Conference, pp. 201–204.

  11. Chungan, P., Dunshan, Y., Xixin, C., & Shimin, S. (2007). A high-performance reconfigurable 2-D transform architecture for H. 264 transform and quantization. 7th International Conference on ASIC, pp. 950–953.

  12. Flynn, M. J., & Oberman, S. F. (2001). Advanced computer arithmetic design. John Wiley & Sons, Inc.

  13. Lee, K. H., & Rim, C. S. (2000). A hardware reduced multiplier for low power design. 2nd IEEE Asia Pacific Conference on ASICs, pp. 331–334.

  14. Cho, K. J., Lee, W. C., Chung, J. G., & Parhi, K. K. (2004). Design of low-error fixed-width modified Booth multiplier. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12, 522–531.

    Article  Google Scholar 

  15. Juang, T. B., & Hsiao, S. F. (2005). Low-error carry-free fixed-width multipliers with low-cost compensation circuits. IEEE Transactions on Circuits and Systems-II, 52, 299–303.

    Article  MathSciNet  Google Scholar 

  16. MacSorley, O. L. (1961). High-speed arithmetic in binary computers. Proceedings of the IRE, 49, 67–91.

    Article  MathSciNet  Google Scholar 

  17. Ruiz, G.A., & Michell, J.A. (2007). Low-cost VLSI architecture design for forward quantization of H.264/AVC. Proceedings 2007 SPIE-The International Society for Optical Engineering, 6590, 65900Y-1–65900P-12.

  18. Huang, Y. W., Hsieh, B. Y., Chen, T. C., & Chen, L. G. (2005). Analysis, fast algorithm, and VLSI architecture design for H.264/AVC intra frame coder. IEEE Transactions on Circuits and Systems for Video Technology, 15(3), 378–401.

    Article  Google Scholar 

  19. Cheng, Z.Y., Chen, C.H., Liu, B.D., Yang, J.F. (2004). High throughput 2-D transform architectures for H.264 advanced video coders. 2004 IEEE Asia-Pacific Conf. on Circuits and Systems, pp. 1141–1144.

  20. Fan, C. P. (2006). Fast 2-Dimensional 4x4 forward integer transform implementation for H.264/AVC. IEEE Transactions on Circuits and Systems, 53(3), 174–177.

    Article  Google Scholar 

  21. Kordasiewicz, R., & Shirani, S. (2007). On hardware implementations of DCT and quantization blocks for H.264/AVC. Journal of VLSI Signal Processing, 47, 93–102.

    Article  Google Scholar 

  22. Pastuszak G. (2008). Transforms and quantization in the high-throughput H.264/AVC encoder based on advanced mode selection. IEEE Computer Society Annual Symposium on VLSI, pp. 203–208.

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Acknowledgments

This work was supported by the Spanish Ministry of Science and Technology (TEC2006-12438).

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Authors and Affiliations

  1. Department of Electronics and Computers, Facultad de Ciencias, University of Cantabria, Avda. De los Castros s/n, Santander, Spain

    G. A. Ruiz & J. A. Michell

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  1. G. A. Ruiz
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  2. J. A. Michell
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Correspondence to G. A. Ruiz.

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Ruiz, G.A., Michell, J.A. Optimized Hardware Implementation for Forward Quantization of H.264/AVC. J Sign Process Syst 72, 35–41 (2013). https://doi.org/10.1007/s11265-012-0693-3

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  • DOI: https://doi.org/10.1007/s11265-012-0693-3

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