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An Efficient Architecture for Sequential Monte Carlo Receivers in Wireless Flat-Fading Channels

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Abstract

A pipelined architecture is developed for a Sequential Monte Carlo (SMC) receiver that performs joint channel estimation and data detection. The promising feature of the proposed SMC receiver is achieving the near-bound performance in fading channels without using any decision feedback, training or pilot symbols. The proposed architecture exploits the parallelism intrinsic to the algorithm and consists of three blocks, i.e., the SMC core, weight calculator, and resampler. Hardware efficient/parallel architectures for each functional block including the resampling block is developed. The novel feature of the proposed architecture is that makes the execution time of the resampling independent of the distributions of the weights. Despite the alternatives in the literature, the proposed scheme achieves a very small execution time by pipelining the resampling and sampling steps. Moreover, it is scalable for high levels of parallelism, has lower memory usage, fixed routing time, and has close to the ideal performance. Finally, an ASIC implementation of the resampling core is presented in a 0.13 μm CMOS technology, which operates at 200 MHz with 0.8 mm2 of silicon area.

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Notes

  1. It is worth mentioning that despite the promising features of the proposed scheme, it may not easily exploit coding gains with soft decision decoding approaches, while modern communication systems often adopt soft-in soft-out detection methods that can jointly perform the channel estimation, equalization, symbol detection, and channel decoding.

  2. Needless to say that the higher latency means the lower sustainable throughput in the hardware.

  3. It is worth mentioning that the fading process is modeled by the output of a 3rd order Butterworth filter driven by a complex white Gaussian noise process. The normalized Doppler frequency was chosen to be 0.1 , which is a fast fading scenario.

  4. The output of the functional simulations of the implemented core using Verilog testbenches.

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Authors and Affiliations

  1. Department of Electrical Engineering, Sharif University of Technology, Tehran, Iran

    Mahdi Shabany

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  1. Mahdi Shabany
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Correspondence to Mahdi Shabany.

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Shabany, M. An Efficient Architecture for Sequential Monte Carlo Receivers in Wireless Flat-Fading Channels. J Sign Process Syst 68, 303–315 (2012). https://doi.org/10.1007/s11265-011-0619-5

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  • DOI: https://doi.org/10.1007/s11265-011-0619-5

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