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Topological Patterns for Scalable Representation and Analysis of Dataflow Graphs

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Abstract

Tools for designing signal processing systems with their semantic foundation in dataflow modeling often use high-level graphical user interfaces (GUIs) or text based languages that allow specifying applications as directed graphs. Such graphical representations serve as an initial reference point for further analysis and optimizations that lead to platform-specific implementations. For large-scale applications, the underlying graphs often consist of smaller substructures that repeat multiple times. To enable more concise representation and direct analysis of such substructures in the context of high level DSP specification languages and design tools, we develop the modeling concept of topological patterns, and propose ways for supporting this concept in a high-level language. We augment the dataflow interchange format (DIF) language—a language for specifying DSP-oriented dataflow graphs—with constructs for supporting topological patterns, and we show how topological patterns can be effective in various aspects of embedded signal processing design flows using specific application examples.

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References

  1. 3GPP TS 36.211 V8.7.0 (2009-05): Physical channels and modulation (2009).

  2. Andrade, H. A., & Kovner, S. (1998). Software synthesis from dataflow models for G and LabVIEW™. In Conference record of the thirty-second Asilomar conference on signals, systems computers (Vol. 2, pp. 1705–1709).

  3. Andrews, J. G., Ghosh, A., & Muhamed, R. (2007). Fundamentals of WiMAX: Understanding broadband wireless networking. Englewood Cliffs: Prentice Hall.

    Google Scholar 

  4. Bhattacharya, B., & Bhattacharyya, S. S. (2000). Parameterized dataflow modeling of DSP systems. In Proceedings of the international conference on acoustics, speech, and signal processing (pp. 1948–1951). Istanbul, Turkey.

  5. Bhattacharyya, S. S., Leupers, R., & Marwedel, P. (2000). Software synthesis and code generation for DSP. IEEE Transactions on Circuits and Systems. 2, Analog and Digital Signal Processing, 47(9), 849–875.

    Article  Google Scholar 

  6. Bhattacharyya, S. S., Murthy, P. K., & Lee, E. A. (1996). Software synthesis from dataflow graphs. Dordrecht: Kluwer Academic.

    Book  MATH  Google Scholar 

  7. Bilsen, G., Engels, M., Lauwereins, R., & Peperstraete, J. A. (1996). Cyclo-static dataflow. IEEE Transactions on Signal Processing, 44(2), 397–408.

    Article  Google Scholar 

  8. Buck, J. T. (1993). Scheduling dynamic dataflow graphs with bounded memory using the token flow model. Ph.D. thesis, EECS Department, University of California, Berkeley. URL http://www.eecs.berkeley.edu/Pubs/TechRpts/1993/2429.html

  9. Cormen, T. H., Leiserson, C. E., Rivest, R. L., & Stein, C. (2001). Introduction to algorithms (2nd ed.). MIT Press and McGraw-Hill.

  10. Corretjer, I., Hsu, C., & Bhattacharyya, S. S. (2006). Configuration and representation of large-scale dataflow graphs using the dataflow interchange format. In Proceedings of the IEEE workshop on signal processing systems (pp. 10–15). Banff, Canada.

  11. Duda, R. O., Hart, P. E., & Stork, D. G. (2000). Pattern classification (2nd ed.). New York: Wiley.

    Google Scholar 

  12. Eker, J., & Janneck, J. W. (2003). CAL language report, language version 1.0—document edition 1. Tech. Rep. UCB/ ERL M03/48, Electronics Research Laboratory, University of California at Berkeley.

  13. Gamma, E., Helm, R., Johnson, R., & Vissides, J. (1995). Design patterns: Elements of reusable object-oriented software. Reading: Addison-Wesley.

    Google Scholar 

  14. Garey, M. R., & Johnson, D. S. (1979). Computers and intractability: A guide to the theory of NP-Completeness. San Francisco: Freeman.

    MATH  Google Scholar 

  15. Haubelt, C., Falk, J., Keinert, J., Schlichter, T., Streubühr, M., Deyhle, A., et al. (2007). A SystemC-based design methodology for digital signal processing systems. EURASIP Journal on Embedded Systems, 2007, Article ID 47580, 22 pp.

  16. Haykin, S. (1996). Adaptive filter theory. Englewood Cliffs: Prentice-Hall.

    Google Scholar 

  17. Hsu, C., Ko, M., & Bhattacharyya, S. S. (2005). Software synthesis from the dataflow interchange format. In Proceedings of the international workshop on software and compilers for embedded systems (pp. 37–49). Dallas, Texas.

  18. Hsu, C., Ramasubbu, S., Ko, M., Pino, J. L., & Bhattacharyya, S. S. (2006). Efficient simulation of critical synchronous dataflow graphs. In Proceedings of the design automation conference (pp. 893–898). San Francisco, California.

  19. Huffman, D. A. (1952). A method for the construction of minimum-redundancy codes. In Proceedings of the IRE (pp. 1098–1101).

  20. Ko, M., Zissulescu, C., Puthenpurayil, S., Bhattacharyya, S. S., Kienhuis, B., & Deprettere, E. (2007). Parameterized looped schedules for compact representation of execution sequences in DSP hardware and software implementation. IEEE Transactions on Signal Processing, 55(6), 3126–3138.

    Article  MathSciNet  Google Scholar 

  21. Kung, S. Y. (1988). VLSI array processors. Englewood Cliffs: Prentice Hall.

    Google Scholar 

  22. Lee, E. A. (1988). Recurrences, iteration, and conditionals in statically scheduled block diagram languages. In Proceedings of the international workshop on VLSI signal processing.

  23. Lee, E. A., & Messerschmitt, D. G. (1987). Static scheduling of synchronous dataflow programs for digital signal processing. IEEE Transactions on Computers, C-36(1), 24–35.

    Article  Google Scholar 

  24. Lee, E. A., & Messerschmitt, D. G. (1988). Digital communication. Dordrecht: Kluwer Academic.

    Book  Google Scholar 

  25. Lee, E. A., & Parks, T. M. (1995). Dataflow process networks. In Proceedings of the IEEE (pp. 773–799).

  26. Oppenheim, A. V., & Schafer, R. W. (1989). Discrete-time signal processing. Englewood Cliffs: Prentice-Hall.

    MATH  Google Scholar 

  27. Pino, J. L., Bhattacharyya, S. S., & Lee, E. A. (1995). A hierarchical multiprocessor scheduling system for DSP applications. In Proceedings of the IEEE Asilomar conference on signals, systems, and computers (Vol.1, pp. 122–126). Pacific Grove, California.

  28. Pino, J. L., & Kalbasi, K. (1998). Cosimulating synchronous DSP applications with analog RF circuits. In Proceedings of the IEEE Asilomar conference on signals, systems, and computers (Vol. 2, pp. 1710–1714). Pacific Grove, California.

  29. Plishker, W., Sane, N., Kiemb, M., Anand, K., & Bhattacharyya, S. S. (2008). Functional DIF for rapid prototyping. In Proceedings of the international symposium on rapid system prototyping (pp. 17–23). Monterey, California.

  30. Sane, N., Hsu, C., Pino, J. L., & Bhattacharyya, S. S. (2010). Simulating dynamic communication systems using the core functional dataflow model. In Proceedings of the international conference on acoustics, speech, and signal processing (pp. 1538–1541). Dallas, Texas.

  31. Sane, N., Kee, H., Seetharaman, G., & Bhattacharyya, S. S. (2010). Scalable representation of dataflow graph structures using topological patterns. In Proceedings of the IEEE workshop on signal processing systems. San Francisco Bay Area, USA.

  32. Shynk, J. J. (1992). Frequency-domain and multirate adaptive filtering. IEEE Signal Processing Magazine, 9(1), 14–37.

    Article  Google Scholar 

  33. Sriram, S., & Bhattacharyya, S. S. (2009). Embedded multiprocessors: Scheduling and synchronization (2nd ed.). Boca Raton: CRC Press.

    Book  Google Scholar 

  34. Stefanov, T., Zissulescu, C., Turjan, A., Kienhuis, B., & Deprettere, E. (2004). System design using Kahn process networks: The Compaan/Laura approach. In Proceedings of the design, automation and test in Europe conference and exhibition (Vol. 1, pp. 340–345).

  35. Sun, W., Wirthlin, M. J., & Neuendorffer, S. (2007). FPGA pipeline synthesis design exploration using module selection and resource sharing. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 26(2), 254–265.

    Article  Google Scholar 

  36. Thies, W., Karczmarek, M., & Amarasinghe, S. (2002). StreamIt: A language for streaming applications. In International conference on compiler construction. Grenoble, France.

  37. Verbauwhede, I. M., Scheers, C. J., & Rabaey, J. M. (1994). Specification and support for multidimensional DSP in the SILAGE language. In IEEE international conference on acoustics, speech, and signal processing (Vol. 2, pp. II/473–II/476). doi:10.1109/ICASSP.1994.389622.

  38. Wallace, G. K. (1992). The JPEG still picture compression standard. IEEE Transactions on Consumer Electronics, 38(1), xviii–xxxiv. doi:10.1109/30.125072.

    Article  Google Scholar 

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Acknowledgements

Authors acknowledge Government’s support in publication of this paper. The material is based upon work funded by the US Air Force Research Laboratory (AFRLFA87501110049), Laboratory for Telecommunication Sciences, National Radio Astronomy Observatory, US National Science Foundation, and Austrian Marshall Plan Foundation. Any opinions, findings, and conclusions or recommendations expressed in this article are those of the authors and do not reflect the views of AFRL, LTS, NRAO, NSF, or AMPF.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, and Institute for Advanced Computer Studies, University of Maryland, College Park, MD, 20742, USA

    Nimish Sane & Shuvra S. Bhattacharyya

  2. National Instruments, Austin, TX, 78759, USA

    Hojin Kee

  3. Air Force Research Laboratory, Rome, NY, USA

    Gunasekaran Seetharaman

Authors
  1. Nimish Sane
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  2. Hojin Kee
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  3. Gunasekaran Seetharaman
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  4. Shuvra S. Bhattacharyya
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Correspondence to Nimish Sane.

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Sane, N., Kee, H., Seetharaman, G. et al. Topological Patterns for Scalable Representation and Analysis of Dataflow Graphs. J Sign Process Syst 65, 229–244 (2011). https://doi.org/10.1007/s11265-011-0610-1

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