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Architecture and Finite Precision Optimization for Layered LDPC Decoders

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Abstract

Layered decoding is known to provide efficient and high-throughput implementation of LDPC decoders. However, two main issues affect performance and area of practical implementations: quantization and memory. Quantization can strongly degrade performance and memory area can constitute up to 70% of the total area of the decoder implementation. This is the case of the DVB-S2,-T2 and -C2 decoders when considering long frames. This paper is then dedicated to the optimization of these decoders. We first focus on the reduction of the number of quantization bits and propose solutions based on the efficient saturation of the channel values, the extrinsic messages and the a posteriori probabilities (APP). We reduce from 6 to 5 the number of quantization bits for the channel and the extrinsic messages and from 8 to 6 the APPs, without introducing any performance loss. We then consider the optimization of the size of the extrinsic memory considering a multiple code rates decoder. The paper finally presents an optimized fixed-point architecture of a DVB-S2 layered decoder and its implementation on an FPGA device.

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Acknowledgements

The authors thank NXP Semiconductors Caen for the funding of the study, the “Région Bretagne” and the “European Funds for Regional Development”(FEDER) for funding materials used in the study.

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Authors and Affiliations

  1. Lab-STICC, CNRS UMR 3192, Université de Bretagne Sud - UEB, BP 92116 - 56 321, Lorient Cedex, France

    Cédric Marchand, Laura Conde-Canencia & Emmanuel Boutillon

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  1. Cédric Marchand
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  2. Laura Conde-Canencia
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  3. Emmanuel Boutillon
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Correspondence to Cédric Marchand.

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Marchand, C., Conde-Canencia, L. & Boutillon, E. Architecture and Finite Precision Optimization for Layered LDPC Decoders. J Sign Process Syst 65, 185–197 (2011). https://doi.org/10.1007/s11265-011-0604-z

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  • DOI: https://doi.org/10.1007/s11265-011-0604-z

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