Abstract
A low power digital signed array multiplier based on a 2-dimensional (2-D) bypassing technique is proposed in this work. When the horizontally (row) or the vertically (column) operand is zero, the corresponding bypassing cells skip redundant signal transitions to avoid unnecessary calculation to reduce power dissipation. An 8×8 signed multiplier using the 2-D bypassing technique is implemented on silicon using a standard 0.18 μm CMOS process to verify power reduction performance. The power-delay product of the proposed 8×8 signed array multiplier is measured to be 31.74 pJ at 166 MHz, which is significantly reduced in comparison with prior works.
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Acknowledgements
This investigation is partially supported by National Science Council under grant NSC 99-2221-E-110-081-MY3 and EZ-10-09-44-98. It is also partially supported by Ministry of Economic Affairs, Taiwan, under grant 99-EC-17-A-01-S1-104, and 99-EC-17-A-19-S1-133. The authors would like to express their deepest gratefulness to Chip Implementation Center of National Applied Research Laboratories, Taiwan, for their thoughtful chip fabrication service.
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Wang, CC., Hsu, CH., Sung, GN. et al. A Signed Array Multiplier with Bypassing Logic. J Sign Process Syst 66, 87–92 (2012). https://doi.org/10.1007/s11265-010-0558-6
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DOI: https://doi.org/10.1007/s11265-010-0558-6