This paper presents interpolation-free fractional-pixel motion estimation (FME) algorithms and efficient hardware prototype of one of the proposed FME algorithms. The proposed algorithms use a mathematical model to approximate the matching error at fractional-pixel locations instead of using the block matching algorithm to evaluate the actual matching error. Hence, no interpolation is required at fractional-pixel locations. The matching error values at integer-pixel locations are used to evaluate the mathematical model coefficients. The performance of the proposed algorithms has been compared with several FME algorithms including the full quarter-pixel search (FQPS) algorithm, which is used as part of the H.264 reference software. The computational cost and the performance analysis show that the proposed algorithms have about 90% less computational complexity than the FQPS algorithm with comparable reconstruction video quality (i.e., approximately 0.2 dB lower reconstruction PSNR values). In addition, a hardware prototype of one of the proposed algorithms is presented. The proposed architecture has been prototyped using the TSMC 0.18 μm CMOS technology. It has maximum clock frequency of 312.5 MHz, at which, the proposed architecture can process more than 70 HDTV 1080p fps. The architecture has only 13,650 gates. The proposed architecture shows superior performance when compared with several FME architectures.
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H.264: Joint Video Team (JVT) of ISO/IEC MPEG, ITU-T VCEG (ISO/IEC JTC1/SC29/WGII, and ITU-T SG16 Q.6, “Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Specification (ITU-T rec. H.264-ISO/IEC 14496-10 AVC),” 7th Meeting, Pattaya, Thailand, March 2003.
Huang, Y.-W., Hsieh, B.-Y., Chien, S.-Y., Ma, S.-Y., & Chen, L.-G. (2006). Analysis and complexity reduction of multiple reference frames motion estimation in H.264/AVC. IEEE Transactions on Circuits and Systems for Video Technology, 16(4), 507–522.
Denolf, K., Blanch, C., Lafruit, G. & Bormans, A. (2002). Initial memory complexity analysis of the AVC CODEC. In Proc. IEEE Workshop on Signal Processing Systems (SIPS ‘02), pp. 222–227.
Chen, T.-C., Chien, S.-Y., Huang, Y.-W., Tsai, C.-H., Chen, C.-Y., Chen, T.-W., et al. (2006). Analysis and architecture design of an HDTV720p 30 Frames/s H.264/AVC encoder. IEEE Transactions on Circuits and Systems for Video Technology, 16(6), 673–688.
Zhou, B., & Chen, J. (2003). A fast two-step search algorithm for half-pixel motion estimation. In Proc. of the 10th IEEE International Conference on Electronics, Circuits and Systems,(ICECS’03), vol. 2, pp. 611–614.
Wong, H. M., Au, O. C., & Chang, A. (2005). Fast sub-pixel inter-prediction—based on the texture direction analysis. In Proc. IEEE International Symposium on Circuits and Systems (ISCAS’05, vol. 6, pp. 5477–5480.
Wei, Z., Jiang, B., Zhang, X., & Chen, Y. (2004). A new full-pixel and sub-pixel motion vector search algorithm for fast block-matching motion estimation in H.264. In Proc. International Conference Image Graphics, pp. 345–348, Dec.
Tourapis, A., & Topiwala, P. (2005). Sub-Pel ME for enhanced predictive zonal search, MPEG/JVT Meeting, Doc. JVT-Q079, Oct.
Wang, Y.-J., Cheng, C.-C., & Chang, T.-S. (2007). A fast algorithm and its VLSI architecture for fractional motion estimation for H.264/MPEG-4 AVC video coding. IEEE Transactions on Circuits and Systems for Video Technology, 17(5), 578–583.
Du, C., He, Y., & Zheng, J. (2003). PPHPS: a parabolic prediction-based, fast half-pixel search algorithm for very low bit-rate moving-picture coding. IEEE Transactions on Circuits and Systems for Video Technology, 13(6), 514–518.
Chen, Z., Du, C., Wang, J., & He, Y. (2002). PPFPS—a paraboloid prediction based fractional pixel search strategy for H.26 L. In Proc. IEEE International Symposium on Circuits and Systems (ISCAS’02), vol. 3, pp. III-9–III-12.
Suh, J. W., & Jeong, J. (2004). Fast sub-pixel motion estimation techniques having lower computational complexity. IEEE Transaction on Consumer Electronic, 50, 968–973.
Chao-Yang, K., Huang-Chih, K., & Youn-Long, L. (2006). High performance fractional motion estimation and mode decision for H.264/AVC. In Proc. IEEE International Conference on Multimedia and Expo, pp. 1241–1244.
Sayed, M., Badawy, W., & Jullien, G. (2009). Low-complexity algorithm for fractional-pixel motion estimation. In Proc. IEEE International Conference on Image Processing (ICIP’09).
Song, Y., Shao, M., Liu, Z., Li, S., Li, L., Ikenaga, T. et al. (2007). H.264/AVC fractional motion estimation engine with computation reusing in HDTV1080P real-time encoding applications. In Proc. IEEE Workshop on Signal Processing Systems, pp. 509–514.
Su, C.-L., Yang, W.-S., Chen, Y.-L., Li, Y., Chen, C.-W., Guo, J.-I. et al. (2006) Low complexity high quality fractional motion estimation algorithm and architecture design for H.264/AVC. In Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS’06), pp. 578–581.
Changqi, Y., Goto, S., & Ikenaga, T. (2006). High performance VLSI architecture of fractional motion estimation in H.264 for HDTV. In Proc. IEEE International Symposium on Circuits and Systems (ISCAS’06), pp. 2605–2608.
Pirsch, P., & Gehrke, W. (1995). VLSI architectures for video compression. in Proc. IEEE International Symposium on Signals, Systems, and Electronics, pp. 49–54.
Pirsch, P., Demassieux, N., & Gehrke, W. (1995). VLSI architectures for video compression: a survey. IEEE Proceedings, 83(2), 220–246.
Jain, R., Parker, A. C., & Park, N. (1992). Predicting system-level area and delay for pipelining and non-pipelining designs. IEEE Transactions Computer-Aided Design, 1, 955–965.
Jeschke, H., Gaedke, K., & Pirsch, P. (1992). Multiprocessor performance for real-time processing of video coding applications. IEEE Transactions on Circuits and Systems for Video Technology, 2, 221–230.
Deng, L., Gao, W., Hu, M. Z., & Ji, Z. Z. (2005). An efficient hardware implementation for motion estimation of AVC standard. IEEE Transactions on Consumer Electronics, 51(4), 1360–1366.
Jong, H. M., Chen, L. G., & Chiueh, T. D. (1994). Parallel architectures for 3-step hierarchical search block matching algorithm. IEEE Transactions on Circuits and Systems for Video Technology, 4(4), 407–416.
Swamy, P. N., Chakrabarti, I., & Ghosh, D. (2002). Architecture for motion estimation using the one-dimensional hierarchical search block-matching algorithm. IEE Proceedings on Computers and Digital Techniques, 149(5), 229–239.
The authors would like to thank Natural Sciences and Engineering Research Council of Canada (NSERC), Alberta Informatics Circle of Research Excellence (iCORE), Canadian Microelectronics Corporation (CMC), Human Resource Canada (HRC), University Research Grant Committee (UGRC) and Department of Electrical and Computer Engineering at University of Calgary for supporting this research.
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Sayed, M.S., Badawy, W. & Jullien, G. Interpolation-Free Fractional-Pixel Motion Estimation Algorithms with Efficient Hardware Implementation. J Sign Process Syst 67, 139–155 (2012). https://doi.org/10.1007/s11265-010-0525-2
- Video coding
- Fractional-pixel motion estimation