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Implementation of W-CDMA Cell Search on a Highly Parallel and Scalable MPSoC

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Abstract

The performance of the W-CDMA cell search algorithm can be significantly improved using homogeneous general purpose Multi-Processor System-on-Chip (MPSoC) architectures. The application also scales well, as the number of processing nodes increases, allowing practical accelerations to become close to the theoretical maximum. In this work we describe a template MPSoC architecture based on multiprocessor computational clusters, called Ninesilica. Each Ninesilica consist of nine processing nodes based on COFFEE RISC architecture. MPSoC inter- and intra-cluster communication are enabled using hierarchical Network-on-Chip with dedicated point to point and broadcast communication services for better performance. Proposed template has been used to instantiate complete systems with one and four Ninesilica clusters, resulting in MPSoCs with respectively 9 and 36 computational nodes. The MPSoCs have been physically prototyped on a FPGA device, and the W-CDMA cell search algorithm has been mapped on both MPSoC platforms. The four Ninesilica MPSoC can execute W-CDMA in 20.5 ms (at 115 MHz, slow mode implementation) with the total speed-up of 24.3X and 3.3X when compared to a single processing core system and to a single Ninesilica cluster, respectively.

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Acknowledgement

Authors would like to thank Stephen Burgess for his invaluable help.

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Correspondence to Roberto Airoldi.

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Airoldi, R., Ahonen, T., Garzia, F. et al. Implementation of W-CDMA Cell Search on a Highly Parallel and Scalable MPSoC. J Sign Process Syst 64, 137–148 (2011). https://doi.org/10.1007/s11265-010-0524-3

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  • DOI: https://doi.org/10.1007/s11265-010-0524-3

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