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A High-Speed Low-Complexity Concatenated BCH Decoder Architecture for 100 Gb/s Optical Communications

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Abstract

This paper presents a two-iteration concatenated Bose-Chaudhuri-Hocquenghem (BCH) code and its high-speed low-complexity two-parallel decoder architecture for 100 Gb/s optical communications. The proposed architecture features a very high data processing rate as well as excellent error correction capability. A low-complexity syndrome computation architecture and a high-speed dual-processing pipelined simplified inversonless Berlekamp-Massey (Dual-pSiBM) key equation solver architecture were applied to the proposed concatenated BCH decoder with an aim of implementing a high-speed low-complexity decoder architecture. Two-parallel processing allows the decoder to achieve a high data processing rate required for 100 Gb/s optical communication systems. Also, the proposed two-iteration concatenated BCH code structure with block interleaving methods allows the decoder to achieve 8.91dB of net coding gain performance at 10−15 decoder output bit error rate to compensate for serious transmission quality degradation. Thus, it has potential applications in next generation forward error correction schemes for 100 Gb/s optical communications.

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Acknowledgement

This research was partly supported by the IT R&D program of the MKE/MKIT [2010-F-010-01] and partly supported by the MKE, Korea, under the ITRC support program supervised by the NIPA (NIPA-2010-C1090-1011-0007)

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  1. School of Information and Communication Engineering, Inha University, Incheon, Republic of Korea

    Kihoon Lee, Han-Gil Kang, Jeong-In Park & Hanho Lee

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  1. Kihoon Lee
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  2. Han-Gil Kang
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  3. Jeong-In Park
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  4. Hanho Lee
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Correspondence to Kihoon Lee.

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Lee, K., Kang, HG., Park, JI. et al. A High-Speed Low-Complexity Concatenated BCH Decoder Architecture for 100 Gb/s Optical Communications. J Sign Process Syst 66, 43–55 (2012). https://doi.org/10.1007/s11265-010-0519-0

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  • DOI: https://doi.org/10.1007/s11265-010-0519-0

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