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Energy-Efficient Double-Edge Triggered Flip-Flop

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Abstract

This paper presents a novel design for a double-edge triggered flip-flop (DETFF). A detailed analysis of the transistors used in the DETFF is carried out to determine the critical path. Therefore, the proposed DETFF employs low-V th transistors at critical paths such that the power-delay product as well as the large area consumption caused by the low-V th transistors can be resolved simultaneously. Therefore, the proposed DETFF fully utilizes the multi-V th scheme provided by advanced CMOS processes without suffering from a large area penalty, slow clock frequency, and poor noise immunity. The proposed design is implemented using a typical 0.18-μm 1P6M CMOS process. The measurement results reveal that the proposed DETFF reduce the power-delay product by at lease 25% (i.e., dissipated energy).

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References

  1. Wang, C.-C., Huang, C.-J., & Tsai, K.-C. (2000). A 1.0 GHz 0.6-μm 8-bit carry lookahead adder using PLA-styled all-N-transistor logic. IEEE Transactions of Circuits and Systems, Part II: Analog and Digital Signal Processing, 47(2), 133–135.

    Article  Google Scholar 

  2. Wang, C.-C., Wu, C.-F., & Tsai, K.-C. (1998). A 1.0 GHz 64-bit high-speed comparator using ANT dynamic logic with two-phase clocking. IEE Proceedings—Computers and Digital Techniques, 145(6), 433–436.

    Article  Google Scholar 

  3. Afghahi, M., & Yuan, J. (1991). Double edge-triggered D-flip-flop for high-speed CMOS circuits. IEEE Journal of Solid-State Circuits, 26(8), 1168–1170.

    Article  Google Scholar 

  4. Johnson, T. A., & Kourtev, I. S. (2001). A single latch, high speed double-edge triggered flip-flop (DETFF). In 2001 IEEE international conference on electronics, circuits, and systems (Vol. 1, pp. 189–192).

  5. Kim, C., & Kang, S.-M. (2002). A low-swing clock double-edge triggered flip-flop. IEEE Journal of Solid-State Circuits, 37(5), 648–652.

    Article  MathSciNet  Google Scholar 

  6. Lu, S. L., & Ercegovac, M. (1990). A novel CMOS implementation of double-edge triggered flip-flops. IEEE Journal of Solid-State Circuits, 25(4), 1008–1010.

    Article  Google Scholar 

  7. Sung, Y. Y., & Chang, R. C. (2004). A novel CMOS double-edge triggered flip-flop for low-power applications. In 2004 IEEE international symposium on circuits & systems (ISCAS’2004) (pp. 665–668).

  8. Wang, J.-S. (1997). A new true-single-phase-clocked double-edge-triggered flip flop for low-power VLSI design. In 1997 IEEE international symposium on circuits & systems (ISCAS’97) (pp. 1986–1989).

  9. Rasouli, S.-H., Khademzadeh, A., Afzali-Kusha, A., & Nourani, M. (2005). Low-power single- and double-edge-triggered flip-flops for high-speed applications. IEE Proceedings. Circuits, Devices and Systems, 152(2), 118–122.

    Article  Google Scholar 

  10. Shu, Y.-H., Tenqchen, S., Sun, M.-C., & Feng, W.-S. (2006). XNOR-based double-edge-triggered flip-flop for two-phase pipelines. IEEE Transactions on Circuits and Systems, 53(2), 138–142.

    Article  Google Scholar 

  11. Goh, W. L., Seng, Y. K., Zhang, W., & Lim, H. G. (2007). A novel static dual edge-trigger flip-flop for high-frequency low-power application. In 2007 International symposium on integrated circuits (ISIC’07) (Vols. 26–28, pp. 208–211).

  12. Lee, T.-J., Chang, T.-Y., & Wang, C.-C. (2009). Wide-range 5.0/3.3/1.8-V I/O buffer using 0.35-m 3.3-V CMOS technology. IEEE Transactions on Circuits and Systems I: Regular Papers, 56(4), 763–772.

    Article  Google Scholar 

  13. Wang, C.-C., Huang, C.-C., Huang, J.-M., Chang, C.-Y., & Li, C.-P. (2008). ZigBee 868/915-MHz modulator/demodulator for wireless personal area network. IEEE Transactions on VLSI Systems, 16(7), 936–939.

    Article  Google Scholar 

  14. Wang, C.-C., Sung, G.-N., & Liu, P.-L. (2008). Power-aware design of an 8-bit pipelining ANT-based CLA using data transition detection. Journal of Signal Processing Systems, 52(2), 127–135.

    Article  Google Scholar 

  15. Oh, C., Kim, S., & Shin, Y. (2009). Timing analysis of dual-edge-triggered flip-flop based circuits with clock gating. In 2009 IEEE international conference on IC design and technology (ICICDT’09) (pp. 59–62).

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Acknowledgements

This research was partially supported by the National Science Council under grant NSC97-2220-E-110-009, the Ministry of Economic Affairs under grant 98-EC-17-A-02-S2-0017, 98-EC-17-A-07-S2-0010, and 98-EC-17-A-01-S1-0104 and the National Health Research Institutes under grant NHRI-EX98-9732EI. The authors would like to thank CIC of NSC for their chip fabrication service.

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Authors and Affiliations

  1. Department of Electrical Engineering, National Sun Yat-Sen University, Kaohsiung, 80424, Taiwan

    Chua-Chin Wang, Gang-Neng Sung, Ming-Kai Chang & Ying-Yu Shen

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  1. Chua-Chin Wang
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  2. Gang-Neng Sung
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  3. Ming-Kai Chang
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  4. Ying-Yu Shen
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Correspondence to Chua-Chin Wang.

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Chua-Chin Wang, Senior Member, IEEE.

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Wang, CC., Sung, GN., Chang, MK. et al. Energy-Efficient Double-Edge Triggered Flip-Flop. J Sign Process Syst 61, 347–352 (2010). https://doi.org/10.1007/s11265-010-0457-x

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  • DOI: https://doi.org/10.1007/s11265-010-0457-x

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