Skip to main content

Advertisement

SpringerLink
Log in

Energy-Efficient Considerations on a Variable-Bitrate PCI-Express Device

  • Published:
Journal of Signal Processing Systems Aims and scope Submit manuscript

Abstract

Dynamic power management has been adopted in many systems to reduce the power/energy consumption by changing the system state dynamically. This paper explores energy efficiency for systems equipped with PCI-Express devices, which are designed for low power consumption and high performance, compared to corresponding PCI devices. We propose dynamic power management mechanism and a management policy for energy-efficient considerations. A case study for a variable-bit-rate local-area-network device under the PCI-Express specification is exploited to provide supports for dynamic packet transmission. Simulation results show that the proposed mechanism and policy would reduce the system energy consumption substantially.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10

Similar content being viewed by others

References

  1. Aydin, H., Melhem, R., Mossé, D., & Mejía-Alvarez, P. (2001). Determining optimal processor speeds for periodic real-time tasks with different power characteristics. In Proceedings of the IEEE EuroMicro conference on real-time systems (pp. 225–232).

  2. Aydin, H., Melhem, R., Mossé, D., & Mejía-Alvarez, P. (2001). Dynamic and aggressive scheduling techniques for power-aware real-time systems. In Proceedings of the 22nd IEEE real-time systems symposium (pp. 95–105).

  3. Bansal, N., Kimbrel, T., & Pruhs, K. (2004). Dynamic speed scaling to manage energy and temperature. In Proceedings of the symposium on foundations of computer science (pp. 520–529).

  4. Brown, J. J., Chen, D. Z., Greenwood, G. W., Hu, X., & Taylor, R. W. (1997). Scheduling for power reduction in a real-time system. In International symposium on low power electronics and design (pp. 84–87).

  5. Chen, J.-J., & Kuo, C.-F. (2007). Energy-efficient scheduling for real-time systems on dynamic voltage scaling (DVS) platforms. In RTCSA (pp. 28–38).

  6. Chen, J.-J., & Kuo, T.-W. (2006). Procrastination for leakage-aware rate-monotonic scheduling on a dynamic voltage scaling processor. In ACM SIGPLAN/SIGBED conference on languages, compilers, and tools for embedded systems (LCTES) (pp. 153–162).

  7. Chen, J.-J., Kuo, T.-W., & Lu, H.-I. (2005). Power-saving scheduling for weakly dynamic voltage scaling devices. In Workshop on algorithms and data structures (WADS) (pp. 338–349).

  8. Chen, J.-J., Kuo, T.-W., & Shih, C.-S., (2005). 1+ϵ approximation clock rate assignment for periodic real-time tasks on a voltage-scaling processor. In The 2nd ACM conference on embedded software (EMSOFT) (pp. 247–250).

  9. Irani, S., Shukla, S., & Gupta, R. (2003). Algorithms for power savings. In Proceedings of the fourteenth annual ACM-SIAM symposium on discrete algorithms (pp. 37–46). Society for Industrial and Applied Mathematics.

  10. Ishihara, T., & Yasuura, H. (1998). Voltage scheduling problems for dynamically variable voltage processors. In Proceedings of the international symposium on low power electronics and design (pp. 197–202).

  11. Jejurikar, R., Pereira, C., & Gupta, R. (2004). Leakage aware dynamic voltage scaling for real-time embedded systems. In Proceedings of the design automation conference (pp. 275–280).

  12. Kwon, W.-C., & Kim, T. (2003). Optimal voltage allocation techniques for dynamically variable voltage processors. In Proceedings of the 40th design automation conference (pp. 125–130).

  13. Benini, L., Bogliolo, A., & Micheli, G.D. (2000). A survey of design techniques for system-level dynamic power management. IEEE transactions on Very Large Scale Integration Systems, 8, 299–316.

    Article  Google Scholar 

  14. Li, M., & Yao, F. F. (2005). An efficient algorithm for computing optimal discrete voltage schedules. SIAM Journal on Computing, 35(3), 658–671.

    Article  MathSciNet  Google Scholar 

  15. Lorch, J. R., & Smith, A. J. (1997). Scheduling techniques for reducing processor energy use in macos. Wireless Networks, 3, 311–324.

    Article  Google Scholar 

  16. Lu, Y.-H., Chung, E.-Y., Simunic, T., Benini, L., & Micheli, G. D. (2000). Quantitative comparison of power management algorithms. In Design Automation and Test in Europe.

  17. Mejía-Alvarez, P., Levner, E., & Mossé, D. (2004). Adaptive scheduling server for power-aware real-time tasks. ACM Transactions on Embedded Computing Systems, 3(2), 284–306.

    Article  Google Scholar 

  18. PCI Bus Power Management Interface Specification 1.1. (1998) December.

  19. PCI Express Base Specification 1.0a. (2003) April.

  20. PCI Local Bus Specification 2.3. (2002) March.

  21. Putting it All Together: Intels Wireless-Internet-on-a-Chip. (2001) June.

  22. Qu, G., & Potkonjak, M. (1999). Power minimization using system-level partitioning of applications with quality of service requirements. In ICCAD (pp. 343–346).

  23. Quan, G., & Hu, X. (2002). Minimum energy fixed-priority scheduling for variable voltage processor. In Proceedings of the design automation and test Europe conference (pp. 782–787).

  24. Rabaey, J. M., Chandrakasan, A., & Nikolic, B. (2002). Digital integrated circuits (2nd ed.). Englewood Cliffs: Prentice Hall.

    Google Scholar 

  25. Shin, D., Kim, J., & Lee, S. (2001). Low-energy intra-task voltage scheduling using static timing analysis. In Proceedings of the 38th conference on design automation (pp. 438–443). New York: ACM.

    Google Scholar 

  26. Shin, Y., & Choi, K. (1999). Power conscious fixed priority scheduling for hard real-time systems. In Proceedings of the 36th ACM/IEEE conference on design automation conference (pp. 134–139). New York: ACM.

    Chapter  Google Scholar 

  27. Shin, Y., & Choi, K. (1999). Power conscious fixed priority scheduling for hard real-time systems. In DAC (pp. 134–139).

  28. Shin, Y., Choi, K., & Sakurai, T. (2000). Power optimization of real-time embedded systems on variable speed processors. In Proceedings of the 2000 IEEE/ACM international conference on computer-aided design (pp. 365–368). Piscataway: IEEE.

    Google Scholar 

  29. Weiser, M., Welch, B., Demers, A., & Shenker, S. (1994). Scheduling for reduced cpu energy. In Symposium on operating systems design and implementation (pp. 13–23).

  30. Yang, C.-Y., Chen, J.-J., & Kuo, T.-W. (2007). Preemption control for energy-efficient task scheduling in systems with a DVS processor and Non-DVS devices. In The 13th IEEE international conference on embedded and real-time computing systems and applications (RTCSA).

  31. Yao, F., Demers, A., & Shenker, S. (1995). A scheduling model for reduced CPU energy. In Proceedings of the 36th annual symposium on foundations of computer science (pp. 374–382). Piscataway: IEEE.

    Google Scholar 

  32. Yun, H.-S., & Kim, J. (2003). On energy-optimal voltage scheduling for fixed-priority hard real-time systems. ACM Transactions on Embedded Computing Systems, 2(3), 393–430, Aug.

    Article  Google Scholar 

Download references

Acknowledgements

We would like to thank Prof. Tei-Wei Kuo at National Taiwan University for his valuable inputs and the reviewers for their valuable feedbacks.

Moreover, this work is supported in part by a grant from the NSC program 96-2219-E-002-005, in part by a grant from the NSC program 95-2221-E-002-093-MY3, and in part by Excellent Research Projects of National Taiwan University, 97R0062-05.

Author information

Authors and Affiliations

  1. Dell Corporation, Taipei, Taiwan

    Yung-Hen Lee

  2. Computer Engineering and Networks Laboratory (TIK), Swiss Federal Institute of Technology Zurich (ETH Zurich), Zurich, Switzerland

    Jian-Jia Chen

  3. Department of Computer Science and Information Engineering and Graduate Institute of Networking and Multimedia, National Taiwan University, Taipei, Taiwan

    Chi-Sheng Shih

Authors
  1. Yung-Hen Lee
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Jian-Jia Chen
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Chi-Sheng Shih
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Jian-Jia Chen.

Additional information

This work was done when Mr. Lee and Mr. Chen were students at National Taiwan University.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Lee, YH., Chen, JJ. & Shih, CS. Energy-Efficient Considerations on a Variable-Bitrate PCI-Express Device. J Sign Process Syst Sign Image Video Technol 59, 57–69 (2010). https://doi.org/10.1007/s11265-008-0280-9

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11265-008-0280-9

Keywords

Search

Navigation