An Architecture for Programmable Multi-core IP Accelerated Platform with an Advanced Application of H.264 Codec Implementation

Abstract

A new integrated programmable platform architecture is presented, with the support of multiple accelerators and extensible processing cores. An advanced application for this architecture is to facilitate the implementation of H.264 baseline profile video codec. The platform architecture employs the novel concept of virtual socket and optimized memory access to increase the efficiency for video encoding. The proposed architecture is mapped on an integrated FPGA device, Annapolis WildCard-II™ or WildCard-4™, for verification. According to the evaluation under different configurations, the results show that the overall performance of the architecture, with the integrated accelerators, can sufficiently meet the real-time encoding requirement for H.264 BP at basic levels, and achieve about 2–5.5 and 1–3 dB improvement, in terms of PSNR, as compared with MPEG-2 MP and MPEG-4 SP, respectively. The architecture is highly extensible, and thus can be utilized to benefit the development of multi-standard video codec beyond the description in this paper.

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Acknowledgement

The authors would like to thank the support from Alberta Informatics Circle of Research Excellence (iCore), Xilinx Inc., Natural Science and Engineering Research Council of Canada (NSERC), Canada Foundation for Innovation (CFI), and the Department of Electrical & Computer Engineering at the University of Calgary.

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Correspondence to Yifeng Qiu.

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Qiu, Y., Badawy, W. & Turney, R. An Architecture for Programmable Multi-core IP Accelerated Platform with an Advanced Application of H.264 Codec Implementation. J Sign Process Syst Sign Image Video Technol 57, 123–137 (2009). https://doi.org/10.1007/s11265-008-0267-6

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Keywords

  • H.264/AVC
  • Video codec
  • Architecture
  • Multi-core
  • Accelerator
  • Virtual socket
  • Motion estimation
  • DCT/Q
  • IDCT/Q-1
  • CAVLC
  • Deblocking