A Hardware Acceleration Platform for Digital Holographic Imaging

Abstract

This paper presents a hardware acceleration platform for image reconstruction in digital holographic imaging. The hardware accelerator executes a computationally demanding reconstruction algorithm which transforms an interference pattern captured on a digital image sensor into visible images. Focus in this work is to maximize computational efficiency, and to minimize the external memory transfer overhead, as well as required internal buffering. The paper presents an efficient processing datapath with a fast transpose unit and an interleaved memory storage scheme. The proposed architecture results in a speedup with a factor 3 compared with the traditional column/row approach for calculating the two-dimensional FFT. Memory sharing between the computational units reduces the on-chip memory requirements with over 50%. The custom hardware accelerator, extended with a microprocessor and a memory controller, has been implemented on a custom designed FPGA platform and integrated in a holographic microscope to reconstruct images. The proposed architecture targeting a 0.13 µm CMOS standard cell library achieves real-time image reconstruction with 20 frames per second.

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Correspondence to Thomas Lenart.

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Lenart, T., Gustafsson, M. & Öwall, V. A Hardware Acceleration Platform for Digital Holographic Imaging. J Sign Process Syst Sign Image Video Technol 52, 297–311 (2008). https://doi.org/10.1007/s11265-008-0161-2

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Keywords

  • digital holography
  • flexible FFT
  • data scaling
  • hybrid floating-point
  • matrix transpose
  • burst oriented memory