Abstract
In this paper, we propose a cost-effective architecture of variable length decoder (VLD) for MPEG-2 and AVS. In order to save the buffer memory between VLD and IDCT and accelerate decoding speed, block-based pipeline buffers are adopted. Inverse scan (IScan) and inverse quantisation (IQ) are also merged into this architecture for cost-effective implementation and for easier system integration. A novel group-based architecture with the optimized look-up table is used for MPEG-2 and a new memory-efficient architecture with mixed memory organization is used for AVS. We use shared modules in both MPEG-2 and AVS as much as possible, such as the flush unit, the buffer controller and the buffers. Moreover, we propose merged IQ scheme and merged RAMs scheme. Based on 0.18 μm CMOS technology, the proposed design consumes about 11.5 K gates at a clock constrain of 125 MHz. The simulation results show that it can achieve real-time decoding, such as HD1080i (1,920 × 1,088 at 30 MHz) format video of AVS and MPEG-2. Furthermore, we propose an effective design of the buffers between VLD and IDCT according to the IDCT architecture, a cost-efficient IQ architecture with full flexibility and an efficient scheme for accelerating VLC decoding.
Similar content being viewed by others
References
ISO CD 11172, “Coding of moving pictures and associated audio for digital storage media at up to about 1.5Mbit/s,” Nov. 1991.
ISO/IEC JTC1/SC29 CD 13818-2, “Generic Coding of Moving Pictures and. Associated Video,” Nov. 1993.
AVS Video Expert Group, “Information Technology—Advanced Audio Video Coding Standard Part 2: Video,” in Audio Video Coding Standard Group of China (AVS), 2003, Dec. AVS-N1063, Dec.
A. Mukherjee, N. Ranganathan and M. Bassiouni, “Efficient VLSI Design for Data Transformations of Tree-based Codes,” IEEE Trans. Circuits Syst., vol. 38, 1991, pp. 306–314.
H. Park and V. K. Prasanna, “Area Efficient VLSI Architectures for Huffman Coding,” IEEE Trans. Circuits Syst., vol. 40, 1993, pp. 568–575.
C.-T. Hsieh and S. P. Kim, “A Concurrent Memory-Efficient VLC Decoder for MPEG Applications,” IEEE Trans. Consumer Electron., vol. 42, 1996, pp. 439–446.
Y. Fukuzawa, K. Hasegawa, H. Hanaki, E. Iwata and T. Yamazaki, “A Programmable VLC Core Architecture For Video Compression DSP,” Proc. IEEE SiPS ’97 Design and Implementation (formerly VLSI SignalProcessing), 1997, pp. 469–478, Nov.
B.-J. Shieh, Y.-S. Lee and C.-Y. Lee, “A New Approach of Group-Based VLC Codec System with Full Table Programmability,” IEEEE Trans. Circuits Syst. Video Technol., vol. 11, no. 2, 2001, pp.210–221.
L. Li and Y. He, “Decoding Algorithms for RVLC/VLC and their LSI Architecture,” Picture Coding Symposium 2004, 2004, pp. 349–353.
C. Guanghua, M. Shiwei, L. Min, C. Jianlin and S. Yong, “A Fast Variable-Length Decoder with Optimized Lookup Tables on FPGA,” Proc. 7th Int Conf Solid-State Integr Circuits Technol, 18–21 Oct, vol. 3, 2004, pp. 1649–1652.
D. Xiao-gang, Q. Dong, H. Yin and Y. Bo, “A VLSI Structure of Variable-Length Decoder Compatible with MPEG2 Standard,” Microelectronics, vol. 29, no. 6, 1999, pp. 428–431 (in Chinese).
S.M. Lei and M.T. Sun, “An entropy coding system for digital HDTV applications,” IEEE Trans. Circuits Syst. Video Technol., vol. 1, 1991, pp. 147–155.
M.T. Sun and S. M. Lei, “A High-Speed Entropy Decoder for HDTV,” in Proc. IEEE 1992 Custom Integrated Circuits Conference, 1992, pp. 26.3.1–26.3.4.
D. Li, L. Yu and J. Dong, “A Decoder Architecture for Advanced Video Coding Standard,” SPIE Proc. of Visual Communications and Image Processing, 2005, pp. 2299–2308.
B. Sheng, W. Gao, D. Xie and D. Wu, “An Efficient VLSI Architecture of VLD for AVS HDTV Decoder,” IEEE Trans. Consum. Electron., vol. 52, no. 2, 2006.
Y. Qu and Y. He, “A Simple and Memory Efficient VLSI Architecture of CA-2D-VLC decoder for AVS,” in Picture Coding Symposium 2006, 2006.
W. Di, G. Wen, H. Mingzeng and J. Zhenzhou, “A VLSI architecture design of CAVLC decoder,” Proc. 5th Int. Conf. ASIC, 21–24 Oct, vol. 2, 2003, pp. 962–965,.
J. Ikara, S. Vassiliadis, J. Takala and P. Liuha, “Multiple-Symbol Parallel Decoding for Variable Length Codes,” IEEE Trans. VLSI Syst., vol. 12, no.7, 2004.
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Qu, Y., Mei, S. & He, Y. A Cost-effective VLD Architecture for MPEG-2 and AVS. J Sign Process Syst Sign Image Video Technol 52, 95–109 (2008). https://doi.org/10.1007/s11265-007-0101-6
Received:
Revised:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s11265-007-0101-6