Abstract
This paper describes the design of a soft decision Viterbi Decoder for orthogonal frequency division multiplexing-based wireless local area networks and evaluates different architectural options by means of their field programmable gate-array (FPGA) implementation. A finite precision analysis has been performed to reduce the data-path widths under the specifications of IEEE 802.11a and Hiperlan/2 standards. Four implementation strategies (register exchange, trace back, trace back with double rate memory read and pointer trace back) for the survivor management unit have been evaluated together with two different normalization methods for the add–compare–select unit. The results of the implementation in FPGA have been given and it is shown that register exchange and pointer trace back architectures with pre-normalization in the add–compare–select unit achieve the best performance. Both architectures can decode 200 Mbps in a Virtex-4 device with lower latency that the conventional trace back one and pointer trace back exhibits the lowest power consumption, these characteristics make them suitable for future multiple-output multiple-input WLAN systems.
Similar content being viewed by others
References
ETSI TS 101 475, “Technical Specification: Broadband Radio Access Networks (BRAN); HIPERLAN Type 2; Physical (PHY) Layer,” ETSI, 2001.
IEEE Std. 802.11, “Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications: High Speed Physical Layer in the 5 GHz Band,” IEEE, 1999.
IEEE 802.11 WG, “Draft PAR for High Throughput Study Group,” IEEE, 2002.
A.J. Viterbi, “Error Bounds for Convolutional Codes and an Asymptotically Optimum decoding Algorithm,” IEEE Trans. Inf. Theory, IT-13, 1967.
J.G.D. Forney, “The Viterbi Algorithm,” Proc. IEEE, vol. 61, no. 3, 1973, pp. 268–278.
F. Angarita, A. Perez-Pascual, T. Sansaloni and J. Valls, “Efficient Mapping on FPGA of a Viterbi Decoder for Wireless LANs,” in IEEE Workshop on Signal Processing Systems Design and Implementation, November 2005, pp. 710–715.
Y. Gang, T. Arslan and A.T. Erdogan, “An Efficient Pre-Traceback Approach for Viterbi Decoding in Wireless Communication,” IEEE International Symposium on Circuits and Systems (ISCAS 2005), vol. 6, May 2005, pp. 5441–5444.
J. Medbo and P. Schramm, “Channel models for HIPERLAN/2,” ETSI/BRAN document no. 3ERI085B, ETSI/BRAN, 1998.
W.-C. Lee, H.-M. Park, K.-J. Kang and K.-B. Kim, “Performance Analysis of Viterbi Decoder Using Channel State Information in COFDM System,” IEEE Trans. Broadcast., vol. 44, no. 4, 1998, pp. 488–496.
M.-Y. Park and W.-C. Lee, “A Demapping Method Using the Pilots in COFDM Systems,” IEEE Trans. Consum. Electron., vol. 44, no. 3, 1998, pp. 1150–1153.
H.-L. Lou, “Linear Distances as Branch Metrics for Viterbi Decoding of Trellis Codes,” Proc. ICASSP, vol. 6, 2000, pp. 3267–3270.
I. Onyszchuk, “Truncation Length for Viterbi Decoder,” IEEE Trans. Commun., vol. 39, no. 7, 1991, pp. 1023–1026.
R.J. McEliece and I.M. Onyszchuk, “Truncation Effects in Viterbi Decoding,” in Proceedings of the IEEE Conference on Military Communications, Boston, MA, October 1989, pp. 39.3.1–29.3.3.
B. Wilkie and B. Cowie, “Viterbi Decoder Block Decoding-Trellis Termination and Tail Biting,” Xilinx Appilcation Note, XAPP551 (1.0), Xilinx, 2005.
D.J. Coggins, “A comparison of Path Memory Techniques for VLSI Viterbi Decoders,” Proc. Of the VLSI 1989, Munich, August 1989, pp. 379–387.
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Angarita, F., Canet, M.J., Sansaloni, T. et al. Architectures for the Implementation of a OFDM-WLAN Viterbi Decoder. J Sign Process Syst Sign Image Video Technol 52, 35–44 (2008). https://doi.org/10.1007/s11265-007-0071-8
Received:
Revised:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s11265-007-0071-8