An Efficient Architecture for a Lifted 2D Biorthogonal DWT

Abstract

This paper presents a new algorithm for a 2D non-separable lifted bi-orthogonal wavelet transform. The algorithm is derived by factoring complementary pairs of wavelet transform 2D filters. The results are efficient architectures for real time signal processing, which do not require transpose memory for the 2D processing of data. The proposed architecture exploits in place implementation, inherit from the algorithm, and can take advantage of both vertical and horizontal parallelism in the direct implementation. The processing in our architecture is scheduled by carefully pipelining the lifted steps, which allows for up to four times faster processing than the direct implementation. The proposed architecture operates at high speed, consumes low power and has reduced computational complexity as compared to previously published filter and lifted based bi-orthogonal wavelet architectures.

This is a preview of subscription content, log in to check access.

References

  1. 1.

    C. Christopoulos, A. Skodras, and T. Ebrahimi, “The JPEG2000 Still Image Coding System: An Overview,” IEEE Transactions on Consumer Electronics, vol. 46, no. 4, 2000, pp. 1103–1127.

    Article  Google Scholar 

  2. 2.

    M.D. Adams and F. Kossentini, “Reversible Integer-to-Integer Wavelet Transforms for Image Compression: Performance Evaluation and Analysis,” IEEE Transactions on Image Processing, vol. 9, no. 6, 2000, pp. 1010–1024.

    MathSciNet  Article  MATH  Google Scholar 

  3. 3.

    S.G. Mallat, “A Theory for Multiresolution Signal Decomposition: The Wavelet Representation,” IEEE Transactions on Pattern Analysis and Machine Intelligence, vol. 11, 1989, pp. 674–693.

    Article  MATH  Google Scholar 

  4. 4.

    I. Daubechies and W. Sweldens, “Factoring Wavelet Transforms in to Lifting Steps,” Journal of Fourier Analysis and Applications, vol. 4, no. 3, 1998, pp. 247–269.

    MathSciNet  Article  MATH  Google Scholar 

  5. 5.

    W. Sweldens, “The Lifting Scheme: A Custom—design construction of biorthognal wavelets,” Journal of Applied and Computational Harmonic Analysis, vol. 3, pp. 186–200, 1996.

    MathSciNet  Article  MATH  Google Scholar 

  6. 6.

    F. Marino, “Efficient High-Speed/Low-Power Pipelined Architecture for the Direct 2-D Discrete Wavelet Transform,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 47, 2000, pp. 1476–1491.

    Article  Google Scholar 

  7. 7.

    F. Marino, “Two Fast Architectures for the Direct 2-D Discrete Wavelet Transform,” IEEE Transactions on Signal Processing, vol. 49, 2001, pp. 1248–1259.

    Article  Google Scholar 

  8. 8.

    C. Chakrabarti and M. Vishwanath, “Efficient Realizations of the Discrete and Continuous Wavelet Transforms: From Single Chip Implementations to Mappings on SIMD Array Computers,” IEEE Transactions on Signal Processing, vol. 43, 1995, pp. 759–771.

    Article  Google Scholar 

  9. 9.

    Chu Yu and Sao-Jie Chen, “Design of an Efficient VLSI Architecture for 2-D Discrete Wavelet Transforms,” IEEE Transactions on Consumer Electronics, vol. 45, 1999, pp. 135–140.

    Article  Google Scholar 

  10. 10.

    M.H. Sheu, M.D. Shieh, and S.W. Liu, “A Low Cost VLSI Architecture Design for Non-Separable 2-D Discrete Wavelet Transform,” in Proc. 40th Midwest Symp. Circuits and Systems, vol. 2, pp. 1217–1220, 1997.

    Google Scholar 

  11. 11.

    H. Meng and Z. Wang, “Fast Spatial Combinative Lifting Algorithm of Wavelet Transform Using the 9/7 Filter for Image Block Compression,” Electronics Letters, vol. 36, 2000, pp. 1766–1767.

    Article  Google Scholar 

  12. 12.

    L. Liu, X. Wang, H. Meng, L. Zhang, Z. Wang, and H. Chen, “A VLSI Architecture of Spatial Combinative Lifting Algorithm Based 2-D DWT/IDWT,” in Asia-Pacific Conference on Circuits and Systems, October 2002, pp. 299–304.

  13. 13.

    Po-Cheng Wu and L. G. Chen, “An Efficient Architecture for Two-Dimensional Discrete Wavelet Transform,” IEEE Transactions on Circuits & Systems for Video Tech., vol. 11, no. 4, 2001.

  14. 14.

    M. Alam, W. Badawy, V. Dimitrov, and G. Jullien, “Efficient Direct 2D Architecture for Lifted Biorthogonal DWT,” IEEE Workshop on Signal Processing Systems, 2003, pp. 340–345.

Download references

Author information

Affiliations

Authors

Corresponding author

Correspondence to Mehboob Alam.

Additional information

M. Alam (Student) is currently M.Sc. student in the Department of Electrical and Computer Engineering at University of Calgary. His research interest includes VLSI signal processing. He is recipient of iCORE International Graduate Scholarship.

Wael Badawy (Ph.D. 00, M.Sc 98, 97; B.Sc. 94) is an associate professor in the Department of Electrical and Computer Engineering. He holds an adjunct professor in the Department of Mechanical Engineering, University of Alberta.

Dr. Badawy’s research interests are in the areas of: Microelectronics, VLSI architectures for video applications with low-bit rate applications, digital video processing, low power design methodologies, and VLSI prototyping. His research involves designing new models, techniques, algorithms, architectures and low power prototype for novel system and consumer products. Dr. Badawy authored and co-authored more than 100 peer reviewed Journal and Conference papers and about 30 technical reports. He is the Guest Editor for the special issue on System on Chip for Real-Time Applications in the Canadian Journal on Electrical and Computer Engineering, the Technical Chair for the 2002 International Workshop on SoC for real-time applications, and a technical reviewer in several IEEE journals and conferences. He is currently a member of the IEEE-CAS Technical Committee on Communication. Dr. Badawy was honored with the “2002 Petro Canada Young Innovator Award”, “2001 Micralyne Microsystems Design Award” and the “1998 Upsilon Pi Epsilon Honor Society and IEEE Computer Society Award for Academic Excellence in Computer Disciplines. He is currently the Chairman of the Canadian Advisor Committee (CAC) and Head of the Canadian Delegation on ISO/IEC/JTC1/SC6 “Telecommunications and Information Exchange Between Systems”. Member, The Canadian Advisory Committee for the Standards Council of Canada-Subcommittee 29: Coding of Audio, Picture Multimedia and Hypermedia Information, and Canadian Delegate, The ISO/IEC MPEG standard committee. He is a voting Member on the VSI Alliance. He is also the Chair of the IEEE-Southern Alberta Society-Computer Chapter.

Vassil S. Dimitrov was born in Plovdiv, Bulgaria, in 1964. He received his Ph.D. degree in mathematics in 1995 from the Mathematical Institute of the Bulgarian Academy of Sciences. Since then, he has spent two years as a postdocral fellow at the VLSI Research Group, University of Windsor, Canada, one year as a research scientist at the Reliable Software Technology Corporation, Virginia, USA, one year as a chief research scientist at the Signal Processing and Computer Technology Laboratory, Helsinki University of Technology, Finland, and one year as an Associate Professor at the University of Windsor, Canada. Since July 2001 he has held the position of Associate Professor at the Department of Electrical and Computer Engineering, University of Calgary, Canada. His main interests are in the area of number theoretic algorithms, computational complexity, cryptography, optimization theory, fast algorithms for digital signal processing and related topics. Dr. Dimitrov is a member of the New York Academy of Sciences.

Graham Jullien (Fellow IEEE) was educated in the United Kingdom, receiving degrees, in Electrical Engineering, from the Universities of Loughborough, Birmingham and Aston (Ph.D., 1969). He was a student engineer and data processing engineer at English Electric Computers, UK, from 1961 to 1966, and a visiting senior research engineer at the Central Research Laboratories of EMI Ltd., UK, from 1975 to 1976. From 1969 until 2000 he was with the Department of Electrical and Computer Engineering at the University of Windsor, Ontario, Canada, where he held the rank of University Professor and was the Director of the VLSI Research Group. Since January 2001, he has been with the Department of Electrical and Computer Engineering at the University of Calgary, where he holds the iCORE Research Chair in Advanced Technology Information Processing Systems. He is a member of the Board of Directors of the Canadian Microelectronics Corporation (CMC) and is a member of the Steering Committee and Board of Directors of the Micronet Network of Centres of Excellence. He has published widely in the fields of Digital Signal Processing, Computer Arithmetic, Neural Networks and VLSI Systems, and teaches courses in related areas. He has served on the technical committees of many international conferences; he currently serves on the Editorial Board of the Journal of VLSI Signal Processing; and is a past Associate Editor of the IEEE Transactions on Computers. He hosted and was program co-chair of the 11th IEEE Symposium on Computer Arithmetic, was program chair for the 8th Great Lakes Symposium on VLSI, and was the technical program chair for the 1999 Asilomar Conference on Signals, Systems and Computers. He is general chair for the 2003 Asilomar Conference and general co-chair of the International Workshop on System-on-Chip for Real-Time Systems, Calgary, Alberta 2003.

Rights and permissions

Reprints and Permissions

About this article

Cite this article

Alam, M., Badawy, W., Dimitrov, V. et al. An Efficient Architecture for a Lifted 2D Biorthogonal DWT. J VLSI Sign Process Syst Sign Image Video Technol 40, 335–342 (2005). https://doi.org/10.1007/s11265-005-5268-0

Download citation

Keywords

  • discrete wavelet transforms
  • lifting
  • biorthogonal transform
  • wavelet architectures
  • image compression
  • lifted architectures
  • Mallat’s algorithms