Abstract
This paper addresses a problem associated with interleaved ADC systems from the digital signal processing algorithm design perspective. The output streams of an interleaved ADC system are inherently in parallel format. It would be nice if DSP algorithms can be designed to take advantage of the inherently parallel signal streams in the interleaved ADC system without the need of a high speed parallel-to-serial multiplexer. Frequency response of a parallel filter bank is derived. It is found that the overall frequency response is the average of each individual interpolated channel filter plus the aliasing components. The aliasing components come from the deviation of each individual channel from the average response.
Results are applied to characterize the gain mismatch of ADC arrays. Sinusoidal response is also investigated. The results can be used to characterize the frequency response mismatch of ADC arrays.
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Yih-Chyun Jenq received the B.S.E. degree from National Taiwan University, Taipei, Taiwan in 1971, and the M.S.E., M.A., and Ph.D. degrees in Electrical Engineering from Princeton University, Princeton, NJ in 1974, 1975, and 1976, respectively. From 1976 to 1980, he was Assistant Professor of Electrical Engineering at the State University of New York at Stony Brook, Stony Brook, NY. From 1980 to 1984, he was a Member of Technical Staff at AT&T Bell Laboratories, Homdel, NJ. From 1984 to 1990, he was a Research Manager and Principal Engineer at Tektronix Laboratories, Beaverton, OR. In September 1990, he joined the Faculty of the Department of Electrical and Computer Engineering at Portland State University, Portland, OR where he is currently a Full Professor. From 1987 to 1989, Dr. Jenq served as Associate Editor of the IEEE Transactions on Circuits and Systems in charge of Digital Signal Processing. He was the recipient of the 1988 Andrew R. Chi Prize Paper Award of the IEEE Instrumentation and Measurement Society. He holds ten (10) U.S. patents. Dr. Jenq is a fellow of the IEEE.
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Jenq, YC. Digital Signal Processing with Interleaved ADC Systems. J VLSI Sign Process Syst Sign Image Video Technol 39, 267–271 (2005). https://doi.org/10.1007/s11265-005-4844-7
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DOI: https://doi.org/10.1007/s11265-005-4844-7