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A New Real Time Object Segmentation and Tracking Algorithm and its Parallel Hardware Architecture

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Abstract

Most of the emerging content-based multimedia technologies are based on efficient methods to solve machine early vision tasks. Among other tasks, object segmentation is perhaps the most important problem in single image processing. The solution of this problem is the key technology of the development of the majority of leading-edge interactive video communication technology and telepresence systems. The aim of this paper is to present a robust framework for real-time object segmentation and tracking in video sequences taken simultaneously from different perspectives. The other contribution of the paper is to present a new dedicated parallel hardware architecture. It’s composed of a mixture of Digital Signal Processing (DSP) and Field Programmable Gate Array (FPGA) technologies and uses the Content Addressable Memory (CAM) as a main processing unit. Experimental results indicate that small amount of hardware can deliver real-time performance and high accuracy. This is an improvement over previous systems, where execution time of the second-order using a greater amount of hardware has been proposed.

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Authors and Affiliations

  1. ECE Department, College of Engineering, SQU University, Muscat, Oman

    Mahmound Meribout

  2. Integrated Information and Energy Laboratories, NTT Corporation, Kanagawa, 243-0192, Japan

    Mamoru Nakanishi

Authors
  1. Mahmound Meribout
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  2. Mamoru Nakanishi
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Corresponding author

Correspondence to Mahmound Meribout.

Additional information

Mahmoud Meribout (BS’85, M’91). Received the PhD degree in Electronic Engineering from the University of Technology of Compiegne (France), in January 3rd 1995. He worked one year as an Associate Researcher, where he has been involved in some industrial projects related to hardware board design and video processing. FromNovember 1995 to October 2000, he has beenworking in Japan, with NTT and NEC corporations respectively, where he has been involved in several projects related to hardware & software design of next generation multimedia and networking equipments. He is holding several Japanese and American patents related to this particular topic. In 1998, he has received the NTT best award for his research and development records.

Maamouru Nakanishi received the B.S. and M.S. in Electronics in 1985 and 1987 respectively, all from Kyoto University. Since 1987, he has been engaged in R&D of parallel processing architectures, memory-processor integration technology at NTT Corporation (Tokyo, Japan), when he has been involved in research on Advanced Content Addressable Memory applied to video processing. In 1998, he has received the NTT best award for his research and development records.

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Meribout, M., Nakanishi, M. A New Real Time Object Segmentation and Tracking Algorithm and its Parallel Hardware Architecture. J VLSI Sign Process Syst Sign Image Video Technol 39, 249–266 (2005). https://doi.org/10.1007/s11265-005-4843-8

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  • DOI: https://doi.org/10.1007/s11265-005-4843-8

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