Abstract
This paper presents a new full-search block-matching algorithm: Multi-stage Interval-based Motion Estimation algorithm (MIME). The proposed algorithm is a block based motion estimation algorithm that utilizes successive elimination technique. We define two approximate functions, as the upper and lower boundaries of the interval that includes the Conventional distortion metric SAD. Each stage in the proposed algorithm; except for the last stage; incorporates low resolution pixels for the boundary functions calculations. The final stage is a full resolution block matching stage. MIME has a high probability of finding the optimal motion vector at any stage of the algorithm. The proposed algorithm reduces the computational complexity by successively eliminating non-candidate blocks from the search window at each stage. This computational reduction leads to enhanced performance in terms of low power consumption and fast motion vector estimation. A low power VLSI implementation of the algorithm is also presented in this paper. Simulation results on benchmark video sequences shows that MIME algorithm eliminates almost 88% of the candidate blocks after only two interval based stages.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
Y. Wang and H. Kuroda, “Hilbert Scanning Search Algorithm for Motion Estimation,” IEEE Transactions on Circuits and Systems for Video Technolog, vol. 9, no. 5, 1999, pp. 683–691.
S. Lee, J. Kim and S. Chae, “New Motion Estimation Algorithm Using Adaptively Quantized Low Bit-Resolution Image and its VLSI Architecture for MPEG2 Video Encoding,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 8, no. 6, 1998, pp 734 –744.
M. Pickering, J. Arnold and M. Frater, “An Adaptive Search Algorithm for Block Matching Motion Estimation,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 7, no. 6, 1997, pp. 906–912.
J.Y. Tham, S. Ranganath, M. Ranganath and A. A. Kassim, “A Novel Unrestricted Center Biased Diamond Search Algorithm for Block Motion Estimation,” IEEE Transactions on Circuits and Systems for Video Technologyy, vol. 8, no. 4, 1998 pp. 369–377.
H. Wang and R.M. Mersereau, “Fast Algorithm for the Estimation of Motion Vectors,”,IEEE Transactions on Image Processingy, vol. 8, no. 3, 1999, pp. 435–438.
J.W. Kim and S. Lee, “Hierarchical Variable Block Size Motion Estimation Technique for Motion Sequence Coding,” Optical Engineeringy, vol. 33, 1994, pp. 2553–2561.
C. Cafforio and F. Rocca, “Methods for Measuring Small Displacements of Television Images,” IEEE Trans. Inform. Thoery, vol. IT-22, no. 5, 1976, pp. 573–579.
M. Tekalp, Digital Video Processing, Prentice-Hall, Englewood Cliffs, NJ, 1995.
J. Jain and A. Jain, “Displacement Measurement and its Applications in Interframe Coding,” IEEE Trans. on Communicationsy, vol. 29, no. 12, 1981, pp. 1799–808.
S. Kim, Y. Kim, K. Kim, H. Chung, K. Choi, Y. Kim, and G. Jung, “A Fast Motion Estimator for Real Time System,” IEEE Trans. on Consumer Electronicsy, vol. 43, no. 1, 1997, pp. 24–33.
W. Badawy and M.A. Bayoumi, “Algorithm-Based Low-Power VLSI Architecture for 2-D Mesh Video-Object Motion Tracking,” IEEE Trans. on Circuits and Systems for Video Technologyy, vol. 12, no. 4, 2002.
L.M. Po and W.C. Ma, “A Novel Four Step Search Algorithm for Fast Block Motion Estimation,” IEEE Trans. on Circuits and Systems for Video Technologyy, vol. 6, 1996, pp. 313–317.
G. Yeh, Y. Lu, and J.Burr, “A Low-Power Video Motion Estimation Array Processor,” in Proceedings of 1996 Symposium on VLSI Circuits Digest of Technical Papers, June 1996, pp. 162–3.
H.A. Mahmoud and Magdy A. Bayoumi, “A 10-Transistor Low-Power High Speed Full Adder Cell,” in Proceedings of IEEE Int. Symp. on Circuits and Systems, ISCASS'99, Orlando, June 1999, pp. 213–216.
W. Li and E. Salari, “Successive Elimination Algorithm for Motion Estimation,” IEEE Transactions on Image Processings, vol. 4, no. 1, 1995, pp 105–107.
V.L. Do and K.Y. Yun, “A Low-Power Architecture for Full-Search Block-Matching Motion Estimation,” IEEE Trans. On Circuits and Systems for Video Technologys, vol. 8, no. 4, 1998, pp. 393–398.
L. He and M. Liou, “Reducing Hardware Complexity of Motion Estimation Algorithms Using Truncated Pixels,” in Proceedings of IEEE International Symposium on Circuits and Systems, ISCAS' 97, Hong Kong, June 1997, pp. 2809–2812.
A. Sousa and N. Roma, “Low-Power Array Architectures for Motion Estimation,” in Proceedings of the IEEE International Workshop on Multimedia Signal Processing, Copenhagen, MMSP' 99, Denmark, Sept. 1999, pp. 679–684.
L. Chan and C. Tsui, “Exploring the Power Consumption of Different Motion Estimation Architectures for Video Compression,” in Proceedings of IEEE International Symposium on Circuits and Systems, ISCAS' 97, Hong Kong, June 1997, pp. 1217–1220.
Author information
Authors and Affiliations
Additional information
Hanan Ahmed Hosny Mahmoud obtained the B.Sc. of Computer Science from Faculty of Engineering, University of Alexandria in 1986. She obtained her M.Sc. in Computer Science from Faculty of Engineering, University of Alexandria in 1991. She obtained the M.Sc. in Computer Engineering from University of Louisiana at Lafayette in 1999 and the Ph.D. in Computer Engineering from University of Louisiana at Lafayette in 2001. Currently, she is working as an Assistant Professor in the Faculty of Engineering, University of Alexandria.
Sumeer Goel received the B. Tech degree in electronics and communications engineering from Punjab Technical University, Punjab, India, in 2001. He received the M.S. degree in computer engineering from University of Louisiana at Lafayette, Lafayette, LA, in 2003 where he is continuing his education towards Ph.D. degree in computer engineering. His research interests are low-power and high noise tolerance VLSI circuit and architecture design for digital signal processing applications.
Mohsen Shaaban received his B.S. degree in electrical engineering and communications from the University of Alexandria, Egypt, in 1998. In 2001, he joined the University of Louisiana at Lafayette (ULL) as a teaching and research assistant at the Center For Advanced Computer Studies (CACS), the VLSI Research Lab. He received his M.S. degree in the field computer engineering from ULL in 2003. Currently, he is pursing his Ph.D. degree in the same field. His research interests include Digital VLSI circuit design, CAD tools and Video processing applications.
Magdy A. Bayoumi received the B.Sc. and M.Sc. degrees in electrical engineering from Cairo University, Cairo, Egypt, in 1973 and 1977, the M.Sc. degree in computer engineering from Washington University in St. Louis, MO, in 1981, and the Ph.D. degree in electrical engineering from the University of Windsor, Windsor, ON, Canada, in 1984.
Currently, he is the Director of the Center for Advanced Computer Studies (CACS), Department Head of the Computer Science Department, the Edmiston Professor of Computer Engineering, and the Lamson Professor of Computer Science at The Center for Advanced Computer Studies, University of Louisiana at Lafayette, where he has been a faculty member since 1985. He has edited and co-edited three books in the area of VLSI Signal Processing. He was an Associate Editor of the Circuits and Devices Magazine and is currently an Associate Editor of Integration, the VLSI Journal, and the Journal of VLSI Signal Processing Systems. He is a Regional Editor for the VLSI Design Journal and on the Advisory Board of the Journal on Microelectronics Systems Integration. He has one patent pending. His research interests include VLSI design methods and architectures, low power circuits and systems, digital signal processing architectures, parallel algorithm design, computer arithmetic, image and video signal processing, neural networks, and wideband network architectures.
Dr. Bayoumi received the University of Louisiana at Lafayette 1988 Researcher of the Year Award and the 1993 Distinguished Professor Award. He was an Associate Editor of the IEEE CIRCUITS AND DEVICES MAGAZINE, the IEEE TRANSACTIONS ON VLSI SYSTEMS, the IEEE TRANSACTIONS ON NEURAL NETWORKS, and the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING. From 1991 to 1994, he served on the Distinguished Visitors Program for the IEEE Computer Society, and he is on the Distinguished Lecture Program of the Circuits and Systems Society. He was the Vice President for the technical activities of the IEEE Circuits and Systems Society. He was the Co-chairman of the Workshop on Computer Architecture for Machine Perception in 1993, and is a member of the Steering Committee of this workshop. He was the General Chairman of the 1994 MWSCAS and is a member of the Steering Committee of this symposium. He was the General Chairman for the 8th Great Lake Symposium on VLSI in 1998. He has been on the Technical Program Committee for ISCAS for several years and he was the Publication Chair for ISCAS'99. He was also the General Chairman of the 2000 Workshop on Signal Processing Design and Implementation. He was a founding member of the VLSI Systems and Applications Technical Committee and was its Chairman. He is currently the Chairman of the Technical Committee on Circuits and Systems for Communication and the Technical Committee on Signal Processing Design and Implementation. He is a member of the Neural Network and the Multimedia Technology Technical Committees. Currently, he is the faculty advisor for the IEEE Computer Student Chapter at the University of Louisiana at Lafayette.
Rights and permissions
About this article
Cite this article
Mahmoud, H., Goel, S., Shaaban, M. et al. A New Efficient Block-Matching Algorithm for Motion Estimation. J VLSI Sign Process Syst Sign Image Video Technol 42, 21–33 (2006). https://doi.org/10.1007/s11265-005-4160-2
Received:
Revised:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s11265-005-4160-2