A real-time scratchpad-centric OS with predictable inter/intra-core communication for multi-core embedded systems

Abstract

Multi-core processors have replaced single-core systems in almost every segment of the industry. Unfortunately, their increased complexity often causes a loss of temporal predictability which represents a key requirement for hard real-time systems. Major sources of unpredictability are shared low level resources, such as the memory hierarchy and the I/O subsystem. In this paper, we approach the problem of shared resource arbitration at an OS-level and propose a novel scratchpad-centric OS design for multi-core platforms. In the proposed OS, the predictable usage of shared resources across multiple cores represents a central design-time goal. Hence, we show (i) how contention-free execution of real-time tasks can be achieved on scratchpad-based architectures, and (ii) how a separation of application logic and I/O operations in time domain can be enforced, and (iii) how predictable asynchronous inter/intra-core communication between tasks can be performed. To validate the proposed design, we implemented the proposed OS using commercial-off-the-shelf (MPC5777M) platform. Experimental results show that novel design delivers predictable temporal behavior to hard real-time tasks, and it provides performance gain of upto \(2.1\,\times \) compared to traditional approaches.

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Notes

  1. 1.

    http://www.qnx.com/products/neutrino-rtos/neutrino-rtos.html.

  2. 2.

    http://www.freertos.org/.

  3. 3.

    http://www.windriver.com/products/vxworks/.

  4. 4.

    We use the terms activation and arrival interchangeably to mean a task release.

  5. 5.

    http://erika.tuxfamily.org/drupal/.

  6. 6.

    http://www.autosar.org/.

  7. 7.

    Applications and OS are compiled using the WindRiver Diab Compiler version 5.9.4—http://www.windriver.com/products/development-tools/.

  8. 8.

    https://www.wireshark.org/.

References

  1. Bai K, Lu J, Shrivastava A, Holton B (2013) CMSM: an efficient and effective code management for software managed multicores. In: Hardware/software codesign and system synthesis (CODES+ ISSS), 2013 international conference on, IEEE, pp 1–9

  2. Betti E, Bak S, Pellizzoni R, Caccamo M, Sha L (2013) Real-time I/O management system with COTS peripherals. IEEE Trans Comput 62(1):45–58

    MathSciNet  Article  Google Scholar 

  3. Bui D, Lee EA, Liu I, Patel H, Reineke J (2011) Temporal isolation on multiprocessing architectures. In: Design automation conference (DAC), pp 274 – 279

  4. Buttazzo GC (2011) Hard real-time computing systems: predictable scheduling algorithms and applications, vol 24. Springer, New York

    Google Scholar 

  5. Chattopadhyay S, Roychoudhury A, Rosén J, Eles P, Peng Z (2014) Time-predictable embedded software on multi-core platforms: analysis and optimization. Found Trends Electron Des Autom 8(3–4):199–356

    Article  Google Scholar 

  6. Deverge J-F, Puaut I (2007) WCET-directed dynamic scratchpad memory allocation of data. In: Real-time systems, 2007. ECRTS’07. 19th Euromicro Conference on, IEEE, pp 179–190

  7. Durrieu G, Faugere M, Girbal S, Perez DG, Pagetti C, Puffitsch W (2014) Predictable flight management system implementation on a multicore processor. In: ERTSS’14

  8. FAA position paper on multi-core processors, CAST-32 (rev 0). http://www.faa.gov/aircraft/air_cert/design_approvals/air_software/cast/cast_papers/media/cast32.pdf. Accessed 26 Jan 2015

  9. Falk H, Kleinsorge JC (2009) Optimal static WCET-aware scratchpad allocation of program code. In: Proceedings of the 46th annual design automation conference, ACM, pp 732–737

  10. Farshchi F, Valsan PK, Mancuso R, Yun H (2018) Deterministic memory abstraction and supporting multicore system architecture

  11. Flodin J, Lampka K, Wang Y (2014) Dynamic budgeting for settling dram contention of co-running hard and soft real-time tasks. In: Industrial embedded systems (SIES), 2014 9th IEEE international symposium on, IEEE, pp 151–159

  12. Girbal S, Jean X, Le Rhun J, Perez DG, Gatti M (2015) Deterministic platform software for hard real-time systems using multi-core COTS. In: Digital avionics systems conference (DASC), 2015 IEEE/AIAA 34th, IEEE, pp 8D4–1

  13. Jean X, Faura D, Gatti M, Pautet L, Robert T (2012) Ensuring robust partitioning in multicore platforms for ima systems. In: Digital avionics systems conference (DASC), 2012 IEEE/AIAA 31st, IEEE, pp 7A4–1

  14. Kai L, Adam L (2016) Resolving contention for networks-on-chips: Combining time-triggered application scheduling with dynamic budgeting of memory bus use. In: International GI/ITG conference on measurement, modelling, and evaluation of computing systems and dependability and fault tolerance, Springer, pp 137–152

  15. Lampka K, Giannopoulou G, Pellizzoni R, Zheng W, Stoimenov N (2014) A formal approach to the wcrt analysis of multicore systems with memory contention under phase-structured task sets. Real Time Syst 50(5–6):736–773

    Article  Google Scholar 

  16. Li L, Gao L, Xue J (2005) Memory coloring: a compiler approach for scratchpad memory management. In: Parallel architectures and compilation techniques, 2005. PACT 2005. 14th international conference on, IEEE, pp 329–338

  17. Lu J, Bai K, Shrivastava A (2013) SSDM: smart stack data management for software managed multicores (SMMs). In: Proceedings of the 50th annual design automation conference, ACM, pp 149

  18. Mancuso R, Dudko R, Betti E, Cesati M, Caccamo M, Pellizzoni R (2013) Real-time cache management framework for multi-core architectures. In: Real-time and embedded technology and applications symposium (RTAS), 2013 IEEE 19th, IEEE, pp 45–54

  19. Mancuso R, Pellizzoni R, Caccamo M, Sha Lui, Yun Heechul (2015) WCET(m) estimation in multi-core systems using single core equivalence. In: Real-time systems (ECRTS), 2015 27th Euromicro conference on, pp 174–183

  20. Metzlaff S, Guliashvili I, Uhrig S, Ungerer T (2011) A dynamic instruction scratchpad memory for embedded processors managed by hardware. In: Architecture of computing systems-ARCS 2011, Springer, pp 122–134

  21. Pellizzoni R, Betti E, Bak S, Yao G, Criswell J, Caccamo M Kegley R (2011) A predictable execution model for COTS-based embedded systems. In: Proceedings of the 2011 17th IEEE real-time and embedded technology and applications symposium, RTAS ’11, IEEE Computer Society, Washington, DC, USA, pp 269–279

  22. Puau I, Pais C (2007) Scratchpad memories vs locked caches in hard real-time systems: a quantitative comparison. In: Design, automation & Test in Europe conference & exhibition, 2007. DATE’07, IEEE, pp 1–6

  23. Schranzhofer A, Pellizzoni R, Chen Jian-Jia, Thiele L, Caccamo M (2010) Worst-case response time analysis of resource access models in multi-core systems. In: Proceedings of the 47th design automation conference, ACM, pp 332–337

  24. Software techniques for scratchpad memory management. http://memsys.io/wp-content/uploads/2015/09/p98-sebexen.pdf. Accessed 26 Jan 2015

  25. Suhendra V, Roychoudhury A, Mitra T (2010) Scratchpad allocation for concurrent embedded software. ACM Trans Program Lang Syst 32(4):13

    Article  Google Scholar 

  26. Tabish R, Mancuso R, Wasly S, Alhammad A, Phatak SS, Pellizzoni R, Caccamo M (2016) A real-time scratchpad-centric os for multi-core embedded systems. In: Real-time and embedded technology and applications symposium (RTAS), 2016 IEEE, IEEE, pp 1–11

  27. Takase H, Tomiyama H, Takada H (2010) Partitioning and allocation of scratch-pad memory for priority-based preemptive multi-task systems. In: Design, automation & test in Europe conference & exhibition (DATE), 2010, IEEE, pp 1124–1129

  28. Ungerer T, Cazorla F, Sainrat P, Bernat G, Petrov Z, Rochange C, Quinones E, Gerdes M, Paolieri M, Wolf J, Casse H, Uhrig S, Guliashvili I, Houston M, Kluge F, Metzlaff S, Mische J (2010) MERASA: multicore execution of hard real-time applications supporting analyzability. IEEE Micro 30(5):66–75

    Article  Google Scholar 

  29. Wasly S, Pellizzoni R (2013) A dynamic scratchpad memory unit for predictable real-time embedded systems. In: Real-time systems (ECRTS), 2013 25th Euromicro Conference on, IEEE, pp 183–192

  30. Wasly S, Pellizzoni R (2014) Hiding memory latency using fixed priority scheduling. In: Real-time and embedded technology and applications symposium (RTAS), 2014 IEEE 20th, IEEE, pp 75–86

  31. Whitham J, Audsley NC (2012) Explicit reservation of local memory in a predictable, preemptive multitasking real-time system. In: Real-time and embedded technology and applications symposium (RTAS), 2012 IEEE 18th, IEEE, pp 3–12

  32. Whitham J, Davis RI, Audsley NC, Altmeyer S, Maiza C (2012) Investigation of scratchpad memory for preemptive multitasking. In: Real-time systems symposium (RTSS), 2012 IEEE 33rd, IEEE, pp 3–13

  33. Wilding MM, Hardin DS, Greve DA (1999) Invariant performance: a statement of task isolation useful for embedded application integration. In: dcca, IEEE, p. 287

  34. Wolf J, Gerdes M, Kluge F, Uhrig S, Mische J, Metzlaff S, Rochange C, Cassé H, Sainrat P, Ungerer T (2010) RTOS support for parallel execution of hard real-time applications on the MERASA multi-core processor. In: Object/component/service-oriented real-time distributed computing (ISORC), 2010 13th IEEE international symposium on, IEEE, pp 193–201

  35. Yun H, Mancuso R, Wu ZP, Pellizzoni R (2014) PALLOC: DRAM bank-aware memory allocator for performance isolation on multicore platforms. In: Real-time and embedded technology and applications symposium (RTAS), 2014 IEEE 20th, IEEE, pp 155–166

  36. Yun H, Yao G, Pellizzoni R, Caccamo M, Sha L (2013) Memguard: memory bandwidth reservation system for efficient performance isolation in multi-core platforms. In: Real-time and embedded technology and applications symposium (RTAS), 2013 IEEE 19th, IEEE, pp 55–64

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Acknowledgements

The material presented in this paper is based upon work supported by the National Science Foundation (NSF) under Grant Numbers CNS-1646383, NSERC 402369-2011 and CMC Microsystems. Marco Caccamo was also supported by an Alexander von Humboldt Professorship endowed by the German Federal Ministry of Education and Research. Any opinions, findings, and conclusions or recommendations expressed in this publication are those of the authors and do not necessarily reflect the views of the NSF and other sponsors.

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Correspondence to Rohan Tabish.

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Tabish, R., Mancuso, R., Wasly, S. et al. A real-time scratchpad-centric OS with predictable inter/intra-core communication for multi-core embedded systems. Real-Time Syst 55, 850–888 (2019). https://doi.org/10.1007/s11241-019-09340-0

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Keywords

  • IPC
  • real-time
  • Predictability
  • Multi-core
  • embedded systems
  • Scratchpad
  • Operating system
  • Inter-core and intra-core communication