Skip to main content
SpringerLink
Log in

Performance debugging of Esterel specifications

  • Published:
Real-Time Systems Aims and scope Submit manuscript

Abstract

Synchronous languages like Esterel have been widely adopted for designing reactive systems in safety-critical domains such as avionics. Specifications written in Esterel are based on the underlying “synchrony hypothesis”, which needs to be validated when Esterel specifications get compiled to real implementations (such as C code). In this work, we present a model-driven and architecture-aware timing analysis framework for C code generated from Esterel and executed on general-purpose processors. By integrating model-level information into the traditional timing analysis, we can efficiently compute accurate time estimates via systematically eliminating a large number of infeasible paths in the generated code. Experimental results show that with our proposed intermediate representation level infeasible path analysis in the model compilation, we obtain up to 16.1 % tighter WCET estimates compared to the traditional assembly code level infeasible path detection with substantially less analysis time. Furthermore, by maintaining the traceability links between Esterel specifications and the generated C code, we are able to map the time-critical computations at the C-level back to the Esterel-level.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Algorithm 1
Fig. 6
Fig. 7
Fig. 8

Similar content being viewed by others

Notes

  1. Subsequent in the sense of the topological order of the control flow DAG.

References

  • AbsInT GmbH (2012) http://www.absint.com/

  • André C (2003) Semantics of synccharts. Technical report, Sophia-Antipolis, France, April 2003

  • Austin TM, Larson E, Ernst D (2002) SimpleScalar: an infrastructure for computer system modeling. IEEE Trans Comput 35(2):59–67

    Google Scholar 

  • Benveniste A, Le Guernic P, Jacquemot C (1991) Synchronous programming with events and relations: the SIGNAL language and its semantics. Sci Comput Program 16(2):103–149

    Article  MathSciNet  MATH  Google Scholar 

  • Benveniste A, Caspi P, Edwards SA, Halbwachs N, Le Guernic P, De Simone R (2003) The synchronous languages 12 years later. Proc IEEE 91(1):64–83

    Article  Google Scholar 

  • Bernhard R, Berry G, Boussinot F, Gonthier G, Ressouche A, Rigault JP, Tanzi JM (June 1991) Programming a Reflex game in Esterel v3. Technical report 07/91, Rapport de Recherche, INRIA, Sophia-Antipolis, France

  • Berry G (1992) Esterel on hardware. In: Mechanized reasoning and hardware design. Prentice-Hall, New York

    Google Scholar 

  • Bertin V, Closse E, Poize M, Pulou J, Sifakis J, Venier P, Weil D, Yovine S (2001) TAXYS = Esterel + Kronos. A tool for verifying real-time properties of embedded systems. In: Proceedings of the 40th IEEE conference on decision and control, vol 3(4–7)

    Google Scholar 

  • Boldt M, Traulsen C, von Hanxleden R (2008) Worst case reaction time analysis of concurrent reactive programs. Electron Notes Theor Comput Sci 203(4):65–79

    Article  Google Scholar 

  • Boussinot F, De Simone R (1991) The Esterel language. Proc IEEE 9(79):1270–1282

    Google Scholar 

  • Chang PY, Hao E, Patt YN (1997) Target prediction for indirect jumps. In: Proceedings of the 24th annual international symposium on computer architecture

    Google Scholar 

  • Edwards SA (2003) The Estbench Esterel benchmark suite. http://www1.cs.columbia.edu/~sedwards/software.html

  • Edwards SA, Zeng J (2007) Code generation in the Columbia Esterel compiler. EURASIP J Embed Syst

  • Ferdinand C (1999) Cache behavior prediction for real-time systems. PhD thesis, Saarland University

  • Ferdinand C et al. (2001) Reliable and precise WCET determination for a real-life processor. In: International conference on embedded software (EMSOFT)

    Google Scholar 

  • Gustafsson J, Ermedahl A, Lisper B (2006) Algorithms for infeasible path calculation. In: International workshop on Worst-Case execution time (WCET) analysis

    Google Scholar 

  • Gustafsson J, Ermedahl A, Sandberg C, Lisper B (2006) Automatic derivation of loop bounds and infeasible paths for wcet analysis using abstract execution. In: IEEE international real-time systems symposium (RTSS)

    Google Scholar 

  • Halbwachs N, Caspi P, Raymond P, Pilaud D (1991) The synchronous dataflow programming language Lustre. Proc IEEE 79(9)

  • Heckmann R et al. (2008) Combining a high-level design tool for safety-critical systems with a tool for WCET analysis on executables. In: 4th European congress on embedded and real time software (ERTS)

    Google Scholar 

  • Ju L, Huynh BK, Roychoudhury A, Chakraborty S (2008) Performance debugging of Esterel specifications. In: International conference on hardware-software codesign and system synthesis (CODES + ISSS)

    Google Scholar 

  • Kuo M, Sinha R, Roop P (2011) Efficient WCRT analysis of synchronous programs using reachability. In: Design automation conference (DAC)

    Google Scholar 

  • Lee C-G et al. (1998) Analysis of cache-related preemption delay in fixed-priority preemptive scheduling. IEEE Trans Comput 47(6):700–713

    Article  MathSciNet  Google Scholar 

  • Li YTS, Malik S (1995) Performance analysis of embedded software using implicit path enumeration. In: ACM SIGPLAN notices, vol 30, pp 88–98

    Google Scholar 

  • Li X, von Hanxleden R (2010) Multi-threaded reactive programming—the Kiel Esterel processor. IEEE Trans Comput

  • Li YTS, Malik S, Wolfe A (1999) Performance estimation of embedded software with instruction cache modeling. ACM Trans Des Autom Electron Syst 4(3):257–279

    Article  Google Scholar 

  • Li X, Lukoschus J, Boldt M, Harder M, Von Hanxleden R (2005) An Esterel processor with full preemption support and its worst case reaction time analysis. In: International conference on compilers, architectures and synthesis for embedded systems (CASES)

    Google Scholar 

  • Li X, Roychoudhury A, Mitra T (2006) Modeling out-of-order processors for wcet analysis. Real-Time Syst 34(3):195–227

    Article  MATH  Google Scholar 

  • Li X et al. (2007) Chronos: A timing analyzer for embedded software. Sci Comput Program 69(1–3):56–67. http://www.comp.nus.edu.sg/~rpembed/chronos

    Article  MATH  Google Scholar 

  • Logothetis G, Schneider K (2003) Exact high level WCET analysis of synchronous programs by symbolic state space exploration. In: Proceedings of the conference on design, automation and test in Europe (DATE)

    Google Scholar 

  • Logothetis G, Schneider K, Metzler C (2003) Exact low-level runtime analysis of synchronous programs for formal verification of real-time systems. In: Forum on design languages (FDL)

    Google Scholar 

  • Logothetis G, Schneider K, Metzler C (2003) Generating formal models for real-time verification by exact low-level runtime analysis of synchronous programs. In: IEEE international real-time systems symposium (RTSS)

    Google Scholar 

  • Mendler M, von Hanxleden R, Traulsen C (2009) WCRT algebra and interfaces for Esterel-style synchronous processing. In: Design, automation and test in Europe (DATE)

    Google Scholar 

  • Negi HS, Mitra T, Roychoudhury A (2003) Accurate estimation of cache-related preemption delay. In: International conference on hardware-software codesign and system synthesis (CODES + ISSS)

    Google Scholar 

  • Potop-Butucaru D, de Simone R, Talpin JP (2004) The synchronous hypothesis and synchronous languages. In: The embedded systems handbook

    Google Scholar 

  • Potop-Butucaru D, Edwards SA, Berry G (2007) Compiling ESTEREL. Springer, Berlin

    Google Scholar 

  • Ringler T (2000) Static worst-case execution time analysis of synchronous programs. In: 5th Ada-Europe international conference. LNCS, vol 1845

    Google Scholar 

  • Roop P, Andalam S, von Hanxleden R, Yuan S, Traulsen C (2009) Tight WCRT analysis for synchronous C programs. In: International conference on compilers, architectures and synthesis for embedded systems (CASES)

    Google Scholar 

  • SCADE Suite (2012) http://www.esterel-technologies.com/products/scade-suite/

  • Shyamasundar RK, Aghav JV (2000) Realizing real-time systems from synchronous language specifications. In: RTSS work-in-progress session

    Google Scholar 

  • Souyris J, Le Pavec E, Himbert G, Jégu V, Borios G, Heckmann R (2005) Computing the worst case execution time of an avionics program by abstract interpretation. In: International workshop on worst-case execution time (WCET) analysis

    Google Scholar 

  • Suhendra V, Mitra T, Roychoudhury A, Chen T (2006) Efficient detection and exploitation of infeasible paths for software timing analysis. In: Design automation conference (DAC)

    Google Scholar 

  • Tan L, Wachter B, Lucas P, Wilhelm R (2009) Improving timing analysis for Matlab Simulink/Stateflow. In: MoDELS’09 ACES-MB workshop

    Google Scholar 

  • von Hanxleden R (2009) SyncCharts in C: a proposal for light-weight, deterministic concurrency. In: International conference on embedded software (EMSOFT)

    Google Scholar 

  • Wilhelm R et al (2008) The worst-case execution time problem—overview of methods and survey of tools. ACM Trans Embed Comput Syst (TECS) 7(3)

  • Yoong LH, Roop P, Salcic Z, Gruian F (2006) Compiling Esterel for distributed execution. In: International workshop on synchronous languages, applications, and programming (SLAP)

    Google Scholar 

  • Yuan S, Andalam S, Yoong LH, Roop PS, Salcic Z (2009) Starpro—a new multithreaded direct execution platform for Esterel. Electron Notes Theor Comput Sci 238(1):37–55

    Article  Google Scholar 

Download references

Acknowledgements

This work was partially supported by A*STAR Public Sector Funding project No. 1121202007, Natural Science Foundation of China (NSFC) grant No. 61070022, Shandong Provincial Natural Science Foundation No. ZR2011FQ036, and Independent Innovation Foundation of Shandong University No. 2011TB018.

Author information

Authors and Affiliations

  1. School of Computer Science and Technology, Shandong University, Shandong, China

    Lei Ju

  2. Department of Computer Science, National University of Singapore, Singapore, Singapore

    Bach Khoa Huynh & Abhik Roychoudhury

  3. Institute for Real-Time Computer Systems, TU Munich, Munich, Germany

    Samarjit Chakraborty

Authors
  1. Lei Ju
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Bach Khoa Huynh
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Abhik Roychoudhury
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Samarjit Chakraborty
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Lei Ju.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Ju, L., Huynh, B.K., Roychoudhury, A. et al. Performance debugging of Esterel specifications. Real-Time Syst 48, 570–600 (2012). https://doi.org/10.1007/s11241-012-9155-z

Download citation

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11241-012-9155-z

Keywords

Search

Navigation