Abstract
The arithmetic and logic unit (ALU) is a key element of complex circuits and an intrinsic part of the most widely recognized complex circuits in digital signal processing. Also, recent attention has been brought to reversible logic and quantum-dot cellular automata (QCA) because of their intrinsic capacity to decrease energy dissipation, which is a crucial need for low-power digital circuits. QCA will be the preferred technology for developing the subsequent generation of digital systems. These technologies played a substantial role in the design of the ALU for operations such as multiplication, subtraction, and division. In developing reversible logic and QCA technologies, the ALU is frequently studied as a central unit. Implementing an efficient ALU with low quantum cost and a small number of cells based on an efficient reversible block can solve all previous issues. Therefore, this research constructs a Feynman gate, a Fredkin gate, and full adder circuits using reversible logic and QCA technology. Using all of the specified circuits, a 20-operation ALU is constructed. The power consumption of the proposed ALU under various energy ranges demonstrated significant improvements over earlier designs.
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References
Ma Q, Xu S (2023) Intentional delay can benefit consensus of second-order multi-agent systems. Automatica 147:110750
Ahmadpour S-S, Mosleh M, Heikalabad SR (2020) An efficient fault-tolerant arithmetic logic unit using a novel fault-tolerant 5-input majority gate in quantum-dot cellular automata. Comput Electr Eng 82:106548
Landauer R (1961) Irreversibility and heat generation in the computing process. IBM J Res Dev 5(3):183–191
Safoev N, Jeon J-C (2020) Design of high-performance QCA incrementer/decrementer circuit based on adder/subtractor methodology. Microprocess Microsyst 72:102927
Lent CS, Tougaw PD (1997) A device architecture for computing with quantum dots. Proc IEEE 85(4):541–557
Safoev N, Jeon J-C (2019) Implementation of high-speed shifting operation in quantum-dot cellular automata technology. Int J Mech Eng Technol 10(2):576–586
Das JC, De D, Mondal SP, Ahmadian A, Ghaemi F, Senu N (2019) QCA based error detection circuit for nano communication network. IEEE Access 7:67355–67366
Khan A, Bahar AN, Arya R (2021) Efficient design of vedic square calculator using quantum dot cellular automata (QCA). IEEE Trans Circuits Syst II Express Briefs 69(3):1587–1591
Maslov D, Dueck GW, Miller DM (2003) Simplification of Toffoli networks via templates. In: Integrated Circuits and Systems Design. SBCCI 2003. Proceedings of 16th Symposium on, 2003. IEEE, pp 53–58
Noorallahzadeh M, Mosleh M, Ahmadpour SS, Pal J, Sen B (2023) A new design of parity preserving reversible Vedic multiplier targeting emerging quantum circuits. Int J Numer Model Electron Netw Devices Fields. https://doi.org/10.1002/jnm.3089
Noorallahzadeh M, Mosleh M, Ahmadpour S-S (2021) Efficient designs of reversible synchronous counters in nanoscale. Circuits Syst Signal Process 40(11):5367–5380
Zhirnov VV, Cavin RK, Hutchby JA, Bourianoff GI (2003) Limits to binary logic switch scaling-a gedanken model. Proc IEEE 91(11):1934–1939
Norouzi M, Heikalabad SR, Salimzadeh F (2020) A reversible ALU using HNG and Ferdkin gates in QCA nanotechnology. Int J Circuit Theory Appl 48(8):1291–1303
Safaiezadeh B, Mahdipour E, Haghparast M, Sayedsalehi S, Hosseinzadeh M (2022) Novel design and simulation of reversible ALU in quantum dot cellular automata. J Supercomput 78(1):868–882
Roy R, Sarkar S, Dhar S (2021) Design and testing of a reversible ALU by quantum cells automata electro-spin technology. J Supercomput 77(12):13601–13628
Goswami M, Sen B, Mukherjee R, Sikdar BK (2017) Design of testable adder in quantum-dot cellular automata with fault secure logic. Microelectron J 60:1–12
Teja VC, Polisetti S, Kasavajjala S (2008) QCA based multiplexing of 16 arithmetic & logical subsystems-a paradigm for nano computing. In: 2008 3rd IEEE International Conference on Nano/Micro Engineered and Molecular Systems. IEEE, pp 758–763
Feynman RP (1986) Quantum mechanical computers. Found Phys 16(6):507–532
Ahmadpour SS, Mosleh M, Heikalabad SR (2018) A revolution in nanostructure designs by proposing a novel QCA full-adder based on optimized 3-input XOR. Phys B Condens Matter 550:383–392
Fredkin E, Toffoli T (1982) Conservative logic. Int J Theor Phys 21(3–4):219–253
Ahmadpour SS, Mosleh M, Rasouli Heikalabad S (2022) Efficient designs of quantum-dot cellular automata multiplexer and RAM with physical proof along with power analysis. J Supercomput 78(2):1672–1695
Abedi D, Jaberipur G, Sangsefidi M (2015) Coplanar full adder in quantum-dot cellular automata via clock-zone-based crossover. IEEE Trans Nanotechnol 14(3):497–504
Shater Mofidi M, Faghih Mirzaee R (2021) Design and evaluation of a carry-skip adder in quantum cellular automata technology. Tabriz J Electr Eng 50(4(94)):1673–1682. https://sid.ir/paper/963521/en
Ahmadpour SS, Mosleh M, Rasouli Heikalabad S (2019) Robust QCA full-adders using an efficient fault-tolerant five-input majority gate. Int J Circuit Theory Appl 47(7):1037–1056
Ahmadpour S-S et al (2022) An efficient and energy-aware design of a novel nano-scale reversible adder using a quantum-based platform. Nano Commun Networks 34:100412
Walus K, Mazur M, Schulhof G, Jullien GA (2005) Simple 4-bit processor based on quantum-dot cellular automata (QCA). In: 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05). IEEE, pp 288–293
Lakshmi SK, Athisha G (2011) Design and analysis of adders using nanotechnology based quantum dot cellular automata. J Comput Sci 7(7):1072
Srivastava S, Asthana A, Bhanja S, Sarkar S (2011) QCAPro-an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 2011. IEEE, pp 2377–2380
Das JC, De D (2016) Quantum-dot cellular automata based reversible low power parity generator and parity checker design for nanocommunication. Front Inf Technol Electron Eng 17(3):224–236
Debnath B, Das JC, De D (2017) Reversible logic-based image steganography using quantum dot cellular automata for secure nanocommunication. IET Circuits Devices Syst 11(1):58–67
Singh G, Sarin RK, Raj B (2017) Design and analysis of area efficient QCA based reversible logic gates. Microprocess Microsyst 52:59–68
Abutaleb M (2018) Robust and efficient QCA cell-based nanostructures of elementary reversible logic gates. J Supercomput 74(11):6258–6274
Thapliyal H, Ranganathan N, Kotiyal S (2012) Design of testable reversible sequential circuits. IEEE Trans Very Large Scale Integr (vlsi) Syst 21(7):1201–1209
Das JC, De D (2017) Nanocommunication network design using QCA reversible crossbar switch. Nano Commun Netw 13:20–33
Arun M, Saravanan S (2013) Reversible arithmetic logic gate (ALG) for quantum computation. Int J Intell Eng Syst 6(3):1–9
Haghparast M, Navi K (2007) A novel reversible full adder circuit for nanotechnology based systems. J Appl Sci 7(24):3995–4000
Biswas P, Gupta N, Patidar N (2014) Basic reversible logic gates and it’s QCA implementation. Int J Eng Res Appl 4(6):12–16
Biswas AK, Hasan MM, Chowdhury AR, Babu HMH (2008) Efficient approaches for designing reversible binary coded decimal adders. Microelectron J 39(12):1693–1703
Hashemi S, Azghadi MR, Navi K (2018) Design and analysis of efficient QCA reversible adders. J Supercomput 75:2106–2125
Hashemi S, Azghadi MR, Navi K (2019) Design and analysis of efficient QCA reversible adders. J Supercomput 75(4):2106–2125
Kumar P, Singh S (2019) Optimization of the area efficiency and robustness of a QCA-based reversible full adder. J Comput Electron 18(4):1478–1489
Ganesh E (1824) Implementation and simulation of arithmetic logic unit, shifter and multiplier in quantum cellular automata technology. Int J Comput Sci Eng 2(5):2010
Waje MG, Dakhole P (2013) Design and implementation of 4-bit arithmetic logic unit using quantum dot cellular automata. In: 2013 3rd IEEE International Advance Computing Conference (IACC). IEEE, pp 1022–1029
Ghosh B, Kumar A, Salimath AK (2013) A simple arithmetic logic unit (12 ALU) design using quantum dot cellular automata. Adv Sci Focus 1(4):279–284
Kanimozhi V (2015) Design and implementation of arithmetic logic unit (ALU) using modified novel bit adder in QCA. In: 2015 International Conference on Innovations in Information, Embedded and Communication Systems (ICIIECS). IEEE, pp 1–6
Antony R, Aravindhan A (2018) Quantum dot cellular automata based arithmetic and logical unit design. Int J Eng Res Technol 7(4):67–72
Pandiammal K, Meganathan D (2018) Design of 8 bit reconfigurable ALU using quantum dot cellular automata. In: 2018 IEEE 13th Nanotechnology Materials and Devices Conference (NMDC). IEEE, pp 1–4
Singh A, Dublish AS, Shreyasi, Naik A, Nithya V (2020) Design and simulation of arithmetic logic unit using quantum dot cellular automata. Int J Electr Eng Technol 11(3):173–180. Available at SSRN: https://ssrn.com/abstract=3636018
Torres FS, Wille R, Niemann P, Drechsler R (2018) An energy-aware model for the logic synthesis of quantum-dot cellular automata. IEEE Trans Comput Aided Des Integr Circuits Syst 37(12):3031–3041
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NJN: Conceptualization, Visualization, Funding acquisition, Formal analysis, Methodology, Writing—original draft, Writing—review & editing. S-SA: Conceptualization, Visualization, Funding acquisition, Formal analysis, Methodology, Writing—original draft, Writing—review & editing. SY: Conceptualization, Visualization, Funding acquisition, Formal analysis, Methodology, Writing—original draft, Writing—review & editing. All authors reviewed the manuscript.
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Navimipour, N.J., Ahmadpour, SS. & Yalcin, S. A nano-scale arithmetic and logic unit using a reversible logic and quantum-dots. J Supercomput 80, 395–412 (2024). https://doi.org/10.1007/s11227-023-05491-x
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DOI: https://doi.org/10.1007/s11227-023-05491-x