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Hardware-accuracy trade-offs for error-resilient applications using an ultra-efficient hybrid approximate multiplier

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Abstract

This paper proposes an ultra-efficient approximate multiplier based on imprecise 4:2 compressors. The proposed approximate multiplier offers hardware-accuracy trade-offs for error-resilient applications using hardware-efficient compressors with different structures in the reduction stages. The significant reduction in the transistor count reduces the area and energy consumption of the proposed design, while the accuracy is more than enough for real-world applications such as neural networks and image processing. The hardware simulations are conducted using HSPICE with the 7 nm tri-gate FinFET model. Moreover, the accuracy criteria are evaluated using MATLAB. Our results indicate that the proposed design improves the power-delay product, energy-delay product, and area, on average, by 74%, 81%, and 56%, compared to the existing counterparts. At the same time, it offers comparable accuracy and quality metrics. This practical compromise between accuracy in different applications and hardware efficiency is evaluated using a comprehensive figure of merit criterion, which is, on average, 75% better in the proposed multiplier than in its counterparts.

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Data availability

The datasets generated during and/or analyzed during the current study are available from the corresponding author on reasonable request.

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  1. Faculty of Electrical Engineering, Shahid Beheshti University, Tehran, Iran

    Sudeh Shirkavand Saleh Abad & Mohammad Hossein Moaiyeri

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  1. Sudeh Shirkavand Saleh Abad
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  2. Mohammad Hossein Moaiyeri
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Correspondence to Mohammad Hossein Moaiyeri.

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Shirkavand Saleh Abad, S., Moaiyeri, M. Hardware-accuracy trade-offs for error-resilient applications using an ultra-efficient hybrid approximate multiplier. J Supercomput 79, 3357–3372 (2023). https://doi.org/10.1007/s11227-022-04789-6

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