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Hybrid learning scenario path selection and abstraction framework for smart verification of complex SoCs

Abstract

The universal verification methodology (UVM) testbench utilizes the bus interface to access the design under verification (DUV) and registers using constraint random access. The UVM testbench is not able to perform cross-platform reusable verification. Alone UVM libraries are non-efficient for cross-platform migration, and individual C package modules are prone to miss corner cases with lower functional coverage. Thus, conventional UVM testbench needs a C test module for target-specific implementation. This work targets the implementation of hybrid UVM-C testbench architecture to potentially implement the auto-survivor path generation on higher integration. This paper proposes the UVM-C testbench model is capable of creating reusable test cases for design and registers with cross-platform communication. The new automation helps in the extraction of input parameters to implement script-based auto-covergroups and basic assertions to improvise functional coverage. The proposed UVM-C model implementation reduces the processing time, module capture value, and simulation time compared to state-of-the-art SystemVerilog and UVM verification methodologies. The method refines the processing time and simulation time by 16.41% and 15.23% as compared to SystemVerilog, while the improvement is 7.89% and 7.44% from UVM. The work also provides an average simulation instance value improvement of 11 per module per testbench run as compared to sole conventional UVM testbench.

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Acknowledgements

This work is supported by the annual contingency grant from the Ministry of Electronics and Information Technology (Meity), Government of India, under grant VISPHD-MEITY-1498.

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Correspondence to Gaurav Sharma.

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Sharma, G., Bhargava, L. & Kumar, V. Hybrid learning scenario path selection and abstraction framework for smart verification of complex SoCs. J Supercomput (2021). https://doi.org/10.1007/s11227-021-04117-4

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Keywords

  • UVM
  • Test case
  • Path selection
  • Register database
  • Coverage closure