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Efficient design and implementation of a robust coplanar crossover and multilayer hybrid full adder–subtractor using QCA technology

Abstract

Quantum dot cellular automaton (QCA) is a novel emerging nanometer-scale-based circuit design using nanocomputing technology, which overcomes the limitations of complementary MOS technology in the precondition of the circuit design area, power, and latency/delay. This paper presents an efficient design of crossover single-layer (coplanar) and multilayer novel hybrid full adder–subtractor circuits by implementing majority gate minimization functional J-map technique. The proposed circuits have been found more efficient in terms of minimum number of QCA cells, low latency, required area in µm2, and reduced quantum cost as compared to existing QCA adder–subtractor designs and also avoid the thermodynamics problems occurring due to long QCA wires with the applied synchronization clocking method. In this paper, we have introduced 14 nm × 14 nm and 16 nm × 16 nm cell size QCA circuits and compared with an existing and proposed novel 18 nm × 18 nm single-layer and multilayer designs. Both designs are implemented by the QCADesigner-E tool with bistable vector and coherent vector energy setup in the Euler method and the Runge–Kutta method.

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References

  1. 1.

    Roohi A, Khademolhosseini H, Sayedsalehi S, Navi K (2014) A symmetric quantum-dot cellular automata design for 5-input majority gate. J Comput Electron 13:701–708. https://doi.org/10.1007/s10825-014-0589-5

    Article  Google Scholar 

  2. 2.

    Bahar AN, Waheed S (2016) Design and implementation of an efficient single layer five input majority voter gate in quantum-dot cellular automata. SpringerPlus 5(636):2–10. https://doi.org/10.1186/s40064-016-2220-7

    Article  Google Scholar 

  3. 3.

    Almatrood A, Singh H (2017) A comparative study of majority/minority logic circuit synthesis methods for post-CMOS nanotechnologies. Engineering 9:890–915. https://doi.org/10.4236/eng.2017.910054

    Article  Google Scholar 

  4. 4.

    Tougaw PD, Lent CS (1994) Logical devices implemented using quantum cellular automata. J Appl Phys 75(3):1818–1825. https://doi.org/10.1063/1.356375

    Article  Google Scholar 

  5. 5.

    Majeed AH, Zainal MSB, Alkaldy E, Nor DM (2020) Full adder circuit design with novel lower complexity xor gate in QCA technology. Trans Electr Electron Mater 21:198–207. https://doi.org/10.1007/s42341-019-00166-y

    Article  Google Scholar 

  6. 6.

    Ahmad F et al (2019) Performance evaluation of an ultra-high speed adder based on quantum-dot cellular automata. Int J Inf Technol 11:467–478

    Google Scholar 

  7. 7.

    Kassa SR, Nagaria RK (2016) A novel design of quantum dot cellular automata 5-input majority gate with some physical proofs. J Comput Electron 15:324–334. https://doi.org/10.1007/s10825-015-0757-2

    Article  Google Scholar 

  8. 8.

    Walus K et al (2004) QCADesigner: a rapid design and simulation tool for quantum-dot cellular automata. IEEE Trans Nanotechnol 3(1):26–31. https://doi.org/10.1109/TNANO.2003.820815

    Article  Google Scholar 

  9. 9.

    Lent C, Tougaw P (1997) A device architecture for computing with quantum dots. Proc IEEE 85(4):541–557. https://doi.org/10.1109/5.573740

    Article  Google Scholar 

  10. 10.

    Sasamal TN, Singh AK, Mohan A (2020) Quantum-dot cellular automata based digital logic circuits: a design perspective. Stud Comput Intell Springer Singapore. https://doi.org/10.1007/978-981-15-1823-2

    Article  MATH  Google Scholar 

  11. 11.

    Sadeghi M, Navi K, Dolatshahi M (2020) Novel efficient full adder and full subtractor designs in quantum cellular automata. J Supercomput 76:2191–2205. https://doi.org/10.1007/s11227-019-03073-4

    Article  Google Scholar 

  12. 12.

    Patidar M, Gupta N (2020) An efficient design of edge-triggered synchronous memory element using quantum dot cellular automata with optimized energy dissipation. J Comput Electron 19:529–542. https://doi.org/10.1007/s10825-020-01457-x

    Article  Google Scholar 

  13. 13.

    Zoka S, Gholami M (2019) A novel efficient full adder–subtractor in QCA nanotechnology. Int Nano Lett 9:51–54. https://doi.org/10.1007/s40089-018-0256-0

    Article  Google Scholar 

  14. 14.

    Lakshmi SK, Athisha G (2011) Design and analysis of adders using nanotechnology based quantum dot cellular automata. J Comput Sci 7:1072–1079. https://doi.org/10.3844/jcssp.2011.1072.1079

    Article  Google Scholar 

  15. 15.

    Ahmad PZ et al (2017) A novel reversible logic gate and its systematic approach to implement cost-efficient arithmetic logic circuits using QCA. Data Brief 15:701–708. https://doi.org/10.1016/j.dib.2017.10.011

    Article  Google Scholar 

  16. 16.

    Sen B, Dutta M, Sikdar BK (2014) Efficient design of parity preserving logic in quantum-dot cellular automata targeting enhanced scalability in testing. Microelectron Eng 45(2):239–248. https://doi.org/10.1016/j.mejo.2013.11.008

    Article  Google Scholar 

  17. 17.

    Chakrabarty R, Mandal NK (2017) Design of a controllable adder-subtractor circuit using quantum dot cellular automata. IOSR J Electr Electron Eng 12(4):44–59. https://doi.org/10.9790/1676-1204034459

    Article  Google Scholar 

  18. 18.

    Barughi YZ, Heikalabad SR (2017) A three-layer full adder/subtractor structure in quantum-dot cellular automata. Int J Theor Phys 56:2848–2858. https://doi.org/10.1007/s10773-017-3453-0

    Article  MATH  Google Scholar 

  19. 19.

    Labrado C, Thapliyal H (2016) Design of adder and subtractor circuits in majority logic-based on filed-coupled QCA nanocompeting. Electron Lett 52(6):464–466. https://doi.org/10.1049/el.2015.3834

    Article  Google Scholar 

  20. 20.

    Mahmoud H (2011) Systematic minimization techniques for majority-majority digital combinational circuits. J Appl Sci 11(5):832–839. https://doi.org/10.3923/jas.2011.832.839

    Article  Google Scholar 

  21. 21.

    Mahmoud-Abd-Alla HA (2008) J-Map for quantum dot cellular automata. In: ISCGAV’08: Proceedings of the 8th conference on Signal processing, computational geometry and artificial vision (ISCGAV’08), pp 177–182

  22. 22.

    Mohammadi M, Gorgin S, Mohammadi M (2017) Design of nano-restoring divider in quantum-dot cellular automata technology. IET Circ Device Syst 11(2):135–141. https://doi.org/10.1109/NANO.2011.6144359

    Article  Google Scholar 

  23. 23.

    Das K, De D, De M (2016) modified ternary Karnaugh map and logic synthesis in ternary quantum dot cellular automata. IETE J Res 62(6):774–785. https://doi.org/10.1080/03772063.2016.1176541

    Article  Google Scholar 

  24. 24.

    Patidar M, Gupta N (2019) Efficient design and simulation of novel exclusive-or gate based on nanoelectronics using quantum-dot cellular automata. Proc Second Int Conf Microelectron Comput Commun Syst Lect Notes Electr Eng Springer Singapore 476:599–614. https://doi.org/10.1007/978-981-10-8234-4_48

    Article  Google Scholar 

  25. 25.

    Torres FS, Wille R, Niemann P, Drechsler R (2018) An energy-aware model for the logic synthesis of quantum-dot cellular automata. IEEE Trans CAD 37(12):3031–3041. https://doi.org/10.1109/TCAD.2018.2789782

    Article  Google Scholar 

  26. 26.

    Kianpour M, Sabbaghi R (2017) Novel 8-bit reversible full adder/subtractor using a QCA reversible gate. J Comput Electron 16(2):459–472. https://doi.org/10.1007/s10825-017-0963-1

    Article  Google Scholar 

  27. 27.

    Hassan MK et al (2017) Dataset demonstrating the temperature effect on average output polarization for QCA based reversible logic gates. Data Brief 13:713–716. https://doi.org/10.1016/j.dib.2017.06.058

    Article  Google Scholar 

  28. 28.

    Abdullah-Al-Shafi M, Bahar AN (2018) An architecture of 2-dimensional 4-dot 2-electron QCA full adder and subtractor with energy dissipation study. Act Passive Electron Compon 2018:1–10. https://doi.org/10.1155/2018/5062960

    Article  Google Scholar 

  29. 29.

    Abdullah-Al-Shafi M, Bahar AN, Chen K (2017) Ultra-efficient design of robust RS flip-flop in nanoscale with energy dissipation study. Cogent Eng 4(1):1–11. https://doi.org/10.1080/23311916.2017.1391060

    Article  Google Scholar 

  30. 30.

    Abdullah-Al-Shafi M, Bahar AN, Ahmad F, Ahmed K (2017) Performance evaluation of efficient combinational logic design using nanomaterial electronics. Cogent Eng 4(1):1–15. https://doi.org/10.1080/23311916.2017.1349539

    Article  Google Scholar 

  31. 31.

    Touil L, Gassoumi I, Laajimi R, Ouni B (2018) Efficient design of BinDCT in quantum-dot cellular automata (QCA) technology. IET Image Proc 12(6):1020–1030. https://doi.org/10.1049/iet-ipr.2017.1116

    Article  Google Scholar 

Download references

Acknowledgements

The authors wish to thank the anonymous referees for their valuable comments and suggestions that contributed to improving the quality of the work in this paper.

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Correspondence to Mukesh Patidar.

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Patidar, M., Gupta, N. Efficient design and implementation of a robust coplanar crossover and multilayer hybrid full adder–subtractor using QCA technology. J Supercomput 77, 7893–7915 (2021). https://doi.org/10.1007/s11227-020-03592-5

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Keywords

  • Hybrid full adder–subtractor (HFAS)
  • J-map
  • Majority gate (MG)
  • Nanocomputational
  • Quantum cell size
  • Quantum dot cellular automata