Skip to main content
SpringerLink
Log in

A prefetch-aware scheduling for FPGA-based multi-task graph systems

  • Published:
The Journal of Supercomputing Aims and scope Submit manuscript

Abstract

In partially run-time reconfigurable (PRR) FPGAs, hardware tasks should be configured before their execution. The configuration delay imposed by the reconfiguration process increases the total execution time of the hardware tasks and task graphs. In this paper, a new technique named forefront-fetch is presented to improve the makespan of hardware task graphs running on PRR FPGAs via alleviating the adverse effects of the configuration delays. In this technique, which is applied to a sequence of task graphs, the configuration of some tasks is carried out within the execution phase of the previous task graph. This strategy leads to hide the configuration delay of the forefront-fetched tasks that as a result improves the execution time. The proposed solution modifies the schedules of the task graphs at design time to obtain a set of schedule pairs for the run-time environment. Experiments on actual and synthesized task graphs demonstrate the ability of the proposed technique in improving the makespan of hardware task graphs. The obtained results show that for a set of task graphs running on Xilinx™ Virtex-5 XUPV5LX110T FPGA, makespan is improved by 37.81% on average. Moreover, the proposed solution outperforms state-of-the-art prefetch-aware scheduling strategies by 14.78% makespan improvement.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9

Similar content being viewed by others

References

  1. Bolchini C, Miele A, Sandionigi C (2013) Autonomous fault-tolerant systems onto SRAM-based FPGA platforms. J Electron Test 29(6):779–793

    Google Scholar 

  2. Galanis MD, Dimitroulakos G, Goutis CE (2006) Performance improvements from partitioning applications to FPGA hardware in embedded SoCs. J Supercomput 35(2):185–199

    Google Scholar 

  3. Say F, Bazlamaçcı CF (2012) A reconfigurable computing platform for real time embedded applications. Microprocess Microsyst 36(1):13–32

    Google Scholar 

  4. Clemente JA, Resano J, González C, Mozos D (2011) A hardware implementation of a run-time scheduler for reconfigurable systems. IEEE Trans Very Large Scale Integr (VLSI) Syst 19(7):1263–1276

    Google Scholar 

  5. Rodríguez A et al (2019) Parallel multiprocessing and scheduling on the heterogeneous Xeon + FPGA platform. J Supercomput 1–21

  6. XilinxCorporation (2019), “Virtex-5 FPGA Configuration User Guide, UG191 (v 3.11),” online at: www.xilinx.com/support/documentation/user_guides/ug191.pdf, 2012

  7. Liu S, Pittman RN, Forin A, Gaudiot J-L (2012) Minimizing the runtime partial reconfiguration overheads in reconfigurable systems. J Supercomput 61(3):894–911

    Google Scholar 

  8. Ghavidel A, Sedaghat Y, Naghibzadeh M (2019) Hybrid scheduling to enhance reliability of real-time tasks running on reconfigurable devices. J Supercomput 1–30

  9. Thoman P et al (2018) A taxonomy of task-based parallel programming technologies for high-performance computing. J Supercomput 74(4):1422–1434

    Google Scholar 

  10. Ramezani R, Sedaghat Y, Naghibzadeh M, Clemente JA (2018) A decomposition-based reliability and makespan optimization technique for hardware task graphs. Reliab Eng Syst Saf 180:13–24

    Google Scholar 

  11. Li K (2018) Energy constrained scheduling of stochastic tasks. J Supercomput 74(1):485–508

    Google Scholar 

  12. Hariharan I, Kannan M (2018) Reducing reconfiguration overheads of a reconfigurable dynamic system using active run-time prediction. J Electr Eng 18(2):349–356

    Google Scholar 

  13. Yoosefi A, Naji HR (2017) A clustering algorithm for communication-aware scheduling of task graphs on multi-core reconfigurable systems. IEEE Trans Parallel Distrib Syst 28(10):2718–2732

    Google Scholar 

  14. Abdi A, Zarandi HR (2018) HYSTERY: a hybrid scheduling and mapping approach to optimize temperature, energy consumption and lifetime reliability of heterogeneous multiprocessor systems. J Supercomput 74(5):2213–2238

    Google Scholar 

  15. Zhou T, Pan T, Bao Z, Watanabe T (2018) A time-based leakage-aware algorithm for task placement and scheduling problem on dynamic reconfigurable FPGA. In 2018 5th International Conference on Systems and Informatics (ICSAI), IEEE, pp 501–506

  16. Minhas UI, Woods R, Karakonstantis G (2019) Evaluation of FPGA partitioning schemes for time and space sharing of heterogeneous tasks. In: International Symposium on Applied Reconfigurable Computing, Springer, New York, pp 334–349

  17. Liu T-W, Liu Y-F, Chen Y-S (2017) Energy-aware run-time task partition and allocation in dynamic partial reconfigurable systems. J Syst Archit 78:55–67

    Google Scholar 

  18. El Cadi AA, Souissi O, Atitallah RB, Belanger N, Artiba A (2018) Mathematical programming models for scheduling in a CPU/FPGA architecture with heterogeneous communication delays. J Intell Manuf 29(3):629–640

    Google Scholar 

  19. Ramezani R, Sedaghat Y, Naghibzadeh M, Clemente JA (2017) Reliability and makespan optimization of hardware task graphs in partially reconfigurable platforms. IEEE Trans Aerosp Electron Syst 53(2):983–994

    Google Scholar 

  20. Jing C, Zhu Y, Li M (2013) Energy-efficient scheduling on multi-FPGA reconfigurable systems. Microprocess Microsyst 37(6–7):590–600

    Google Scholar 

  21. Iturbe X (2013) Design and implementation of a reliable reconfigurable real-time operating system (R3TOS). Ph.D. Thesis, University of Edinburgh

  22. Resano J, Mozos D, Catthoor F (2005) A hybrid prefetch scheduling heuristic to minimize at run-time the reconfiguration overhead of dynamically reconfigurable hardware. In: Conference on Design, Automation and Test in Europe, IEEE Computer Society, pp 106–111

  23. Li Z, Hauck S (2002) Configuration prefetching techniques for partial reconfigurable coprocessor with relocation and defragmentation. In: 10th International Symposium on Field-programmable Gate Arrays, ACM/SIGDA, pp 187–195

  24. Clemente JA, Beretta I, Rana V, Atienza Alonso D, Sciuto D (2014) A mapping-scheduling algorithm for hardware acceleration on reconfigurable platforms. ACM Trans Reconfigurable Technol Syst (TRETS) 7(2):636–662

    Google Scholar 

  25. Lu Y, Marconi T, Bertels K, Gaydadjiev G (2009) Online task scheduling for the FPGA-based partially reconfigurable systems. In: International Workshop on Applied Reconfigurable Computing, Springer, New York, pp 216–230

  26. Clemente JA, Resano J, Mozos D (2014) An approach to manage reconfigurations and reduce area cost in hard real-time reconfigurable systems. ACM Trans Embed Comput Syst (TECS) 13(4):1823–1846

    Google Scholar 

  27. Dorflinger A et al (2018) Hardware and software task scheduling for ARM-FPGA platforms. In: 2018 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), IEEE, pp 66–73

  28. Charitopoulos G, Koidis I, Papadimitriou K, Pnevmatikatos D (2017) Run-time management of systems with partially reconfigurable FPGAs. Integration 57:34–44

    Google Scholar 

  29. Vipin K, Fahmy SA (2018) FPGA dynamic and partial reconfiguration: A survey of architectures, methods, and applications. ACM Comput Surv (CSUR) 51(4):72

    Google Scholar 

  30. Hariharan I, Kannan M (2019) Reducing reconfiguration overheads using configuration prefetch, optimal reuse, and optimal memory mapping. Natl Acad Sci Lett 1–5

  31. Steiger C, Walder H, Platzner M (2004) Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks. IEEE Trans Comput 53(11):1393–1407

    Google Scholar 

  32. Guan N, Deng Q, Gu Z, Xu W, Yu G (2008) Schedulability analysis of preemptive and nonpreemptive EDF on partial runtime-reconfigurable FPGAs. ACM Trans Des Autom Electron Syst (TODAES) 13(4):1792–1834

    Google Scholar 

  33. Wang Y, Hoe JC, Nurvitadhi E (2019) Processor assisted worklist scheduling for FPGA accelerated graph processing on a shared-memory platform. In: 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), IEEE, pp 136–144

  34. Ramezani R, Sedaghat Y, Clemente JA (2017) Reliability improvement of hardware task graphs via configuration early fetch. IEEE Trans Very Large Scale Integr (VLSI) Syst 25(4):1408–1420

    Google Scholar 

  35. Al-Sharaeh S, Wells BE (1996) A comparison of heuristics for list schedules using the Box-method and P-method for random digraph generation. In: 28th Southeastern Symposium on System Theory, IEEE, pp 467–471

  36. Danne K, Platzner M (2006) An EDF schedulability test for periodic tasks on reconfigurable hardware devices. In: ACM SIGPLAN notices, vol 41, No. 7, ACM, pp 93–102

  37. Steiger C, Walder H, Platzner M, Thiele L (2003) Online scheduling and placement of real-time tasks to partially reconfigurable devices. In: 24th Real-Time Systems Symposium (RTSS), IEEE, pp 224–225

Download references

Author information

Authors and Affiliations

  1. Department of Software Engineering, Faculty of Computer Engineering, University of Isfahan, Isfahan, Iran

    Reza Ramezani

Authors
  1. Reza Ramezani
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Reza Ramezani.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Ramezani, R. A prefetch-aware scheduling for FPGA-based multi-task graph systems. J Supercomput 76, 7140–7160 (2020). https://doi.org/10.1007/s11227-020-03153-w

Download citation

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11227-020-03153-w

Keywords

Search

Navigation