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A methodology correlating code optimizations with data memory accesses, execution time and energy consumption

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Abstract

The advent of data proliferation and electronic devices gets low execution time and energy consumption software in the spotlight. The key to optimizing software is the correct choice, order as well as parameters of optimization transformations that has remained an open problem in compilation research for decades for various reasons. First, most of the transformations are interdependent and thus addressing them separately is not effective. Second, it is very hard to couple the transformation parameters to the processor architecture (e.g., cache size) and algorithm characteristics (e.g., data reuse); therefore, compiler designers and researchers either do not take them into account at all or do it partly. Third, the exploration space, i.e., the set of all optimization configurations that have to be explored, is huge and thus searching is impractical. In this paper, the above problems are addressed for data-dominant affine loop kernels, delivering significant contributions. A novel methodology is presented reducing the exploration space of six code optimizations by many orders of magnitude. The objective can be execution time (ET), energy consumption (E) or the number of L1, L2 and main memory accesses. The exploration space is reduced in two phases: firstly, by applying a novel register blocking algorithm and a novel loop tiling algorithm and secondly, by computing the maximum and minimum ET/E values for each optimization set. The proposed methodology has been evaluated for both embedded and general-purpose CPUs and for seven well-known algorithms, achieving high memory access, speedup and energy consumption gain values (from 1.17 up to 40) over gcc compiler, hand-written optimized code and Polly. The exploration space from which the near-optimum parameters are selected is reduced from 17 up to 30 orders of magnitude.

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Notes

  1. This is an extension of the conference paper ‘A methodology for efficient code optimizations and memory management’, ACM International Conference on Computing Frontiers 2018.

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Acknowledgements

This work is partly supported by the European Commission under H2020-ICT-20152 Contract 687584—Transparent heterogeneous hardware Architecture deployment for eNergy Gain in Operation (TANGO) project.

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  1. University of Plymouth, Plymouth, UK

    Vasilios Kelefouras

  2. University of Leeds, Leeds, UK

    Karim Djemame

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Correspondence to Vasilios Kelefouras.

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Kelefouras, V., Djemame, K. A methodology correlating code optimizations with data memory accesses, execution time and energy consumption. J Supercomput 75, 6710–6745 (2019). https://doi.org/10.1007/s11227-019-02880-z

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