The Journal of Supercomputing

, Volume 74, Issue 7, pp 3193–3210 | Cite as

Efficient implementation of space–time adaptive processing for adaptive weights calculation based on floating point FPGAs

  • Narjes Hasanikhah
  • Siavash Amin-Nejad
  • Ghafar Darvish
  • M. R. Moniri


Space–time adaptive processing (STAP) has an enormous computational complexity which has confined its practical applications. In this paper, we present an implementation based on field programmable gate array (FPGA) for the most computationally intensive portion of STAP, which is the adaptive weights calculation. This involves solving a set of linear equations that uses the radar return data. In the proposed architecture, QR decomposition block is the most computationally part which is parameterized by vector size to create a trade-off between the hardware resources consumption and delay. To achieve an efficient and high-speed structure, the architecture is simulated and implemented in two cases: single-vector and multi-vector. Results show that the calculation time of weights in single-vector design is less than that of multi-vector case. The delay of weights for 6 × 8 × 120 data cube using vector size of 17 and the maximum clock frequency of 259 MHz is 139 μs, and GFLOPs/Watt is 3.89 for implementation on Arria 10 floating point FPGA. Therefore, the presented approach can realize the real-time requirement and floating point computation of the adaptive weights for STAP.


Adaptive weights Cell under test (CUT) Field programmable gate array (FPGA) Implementation QR decomposition (QRD) Space–time adaptive processing (STAP) 


  1. 1.
    Charitopoulos G, Koidis I, Papadimitriou K, Pnevmatikatos D (2017) Run-time management of systems with partially reconfigurable FPGAs. Integr VLSI J 57:34–44. CrossRefGoogle Scholar
  2. 2.
    Klemm R (2002) Principles of space–time adaptive processing. IEE radar, sonar, navigation and avionics. IEE Press, LondonGoogle Scholar
  3. 3.
    Melvin WL (2004) A stap overview. IEEE Aerosp Electron Syst Mag 19(1):19–35. CrossRefGoogle Scholar
  4. 4.
    Richards MA (2005) Fundamentals of radar signal processing. Tata McGraw-Hill Education, New YorkGoogle Scholar
  5. 5.
    Guerci JR (2003) Space time adaptive processing for radar. Artech House, NorwoodGoogle Scholar
  6. 6.
    Gawande NA, Manzano JB, Tumeo A, Tallent NR, Kerbyson DJ, Hoisie A (2015) Power and performance trade-offs for space time adaptive processing. In: IEEE 26th International Conference on Application-Specific Systems, Architectures and Processors, (2015).
  7. 7.
    Paulus AS, Melvin WL, Himed B (2016) Performance and computational trades for RD-STAP algorithms in challenging detection environments. In: IEEE Radar Conference (RadarConf, 2016).
  8. 8.
    Lebak JM, Bojanczyk AW (2000) Design and performance evaluation of a portable parallel library for space–time adaptive processing. IEEE Trans Parallel Distrib Syst 11(3):287–298. CrossRefGoogle Scholar
  9. 9.
    Choudhary A, Liao W-K, Weiner D, Varshney P, Linderman R, Linderman M (2000) R. Brown, Design, implementation and evaluation of parallel pipelined STAP on parallel computers. IEEE Trans Aerosp Electron Syst 36(2):528–548. CrossRefGoogle Scholar
  10. 10.
    Liao WK, Choudhary A, Weiner D, Varshney P (2005) Performance evaluation of a parallel pipeline computational model for space–time adaptive processing. J Supercomput 31(2):137–160. CrossRefzbMATHGoogle Scholar
  11. 11.
    Rajan K, Patnik LM (2003) Implementation of STAP algorithms on IBM SP2 and on ADSP 21062 dual digital signal processor systems. Microprocess Microsyst 27(4):221–227CrossRefGoogle Scholar
  12. 12.
    Shao Y-B, Wang Y-L, Dend Y, Li Q (2006) The universal implementation of space–time adaptive processing. In: International Conference on Radar (2006),
  13. 13.
    Xikun F, Yongliang W (2006) Real-time implementation of airborne radar space–time adaptive processing on multi-DSP system. In: International Conference on Radar (2006).
  14. 14.
    Dikmese S, Kavak A, Kucuk K, Sahin S, Tangel A, Dincer H (2010) Digital signal processor against field programmable gate array implementations of space–code correlator beamformer for smart antennas. IET Microw Antennas Propag 4(5):593–599. CrossRefGoogle Scholar
  15. 15.
    Dikmese S, Kavak A, Kucuk K, Sahin S, Tangel A (2011) FPGA based implementation and comparison of beamformers for CDMA2000. Wireless Pers Commun 57(2):233–253. CrossRefGoogle Scholar
  16. 16.
    Mahmood ZU, Alam M, Jamil K, Al-Hekail ZO (2013) FPGA implementation of space–time adaptive processing (stap) algorithm for target detection in passive radars. In: Progress in Electromagnetics Research C 35: 35–48 (2013).
  17. 17.
    Jarrah A, Jamali M (2013) Software tool for efficient FPGA design of direct data domain approach for space–time adaptive processing. Electron Lett 49(13):789–791. CrossRefGoogle Scholar
  18. 18.
    Li Q, Cao JS, Pei X (2014) Real-time and extensible calculation of STAP weights on FPGA. In: 12th International Conference on Signal Processing (ICSP) 425–428 (2014).
  19. 19.
    Reed IS, Mallett JD, Brennan LE (1974) Rapid convergence rate in adaptive arrays. IEEE Trans Aerosp Electron Syst AES 10(6):853–863. CrossRefGoogle Scholar
  20. 20.
    Tang B, Zhang Y, Tang J, Peng Y (2013) Close form maximum likelihood covariance matrix estimation under a knowledge-aided constraint. IET Radar Sonar Navig 7(8):904–913. CrossRefGoogle Scholar
  21. 21.
    Tong Y, Wang T, Wu J (2015) Improving EFA-STAP performance using persymmetric covariance matrix estimation. IEEE Trans Aerosp Electron Syst 51(2):924–936. CrossRefGoogle Scholar
  22. 22.
    Fuyu T, Tong W, Jianxin W, Bowen L (2016) Improved accuracy of estimated covariance matrix with a novel approach based on STAP. In: IEEE International Conference on Signal Processing, Communications and Computing (ICSPCC, 2016).
  23. 23.
    Langhammer M (2008) High performance matrix multiply using fused datapath operators. In: 42nd Asilomar Conference on Signals, Systems and Computers, (Proceeding of IEEE, 2008) 153–159.
  24. 24.
    Jervis M (2010) Advances in DSP design tool flows for FPGAs. In: Military Communications Conference (2010) 2041–2046.
  25. 25.
    Golub GH, Van Loan CF (1996) Matrix computations, 3rd edn. Johns Hopkins University Press, BaltimorezbMATHGoogle Scholar
  26. 26.
    Woods R, McAllister J, Lightbody G, Yi Y (2008) FPGA-based implementation of signal processing systems. Wiley, LondonCrossRefGoogle Scholar
  27. 27.
    Ming Dong H, Jian Shu C (2013) Recursive KA-STAP algorithm based on QR decomposition. In: International Workshop on Microwave and Millimeter Wave Circuits and System Technology (MMWCST, 2013) 391–394.
  28. 28.
    Merchant F, Vatwani T, Chattopadhyay A, Raha S, Nandy SK, Narayan R (2016) Achieving efficient QR factorization by algorithm-architecture co-design of householder transformation. In: 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems (2016) 98–103.
  29. 29.
    Bin S, Shaohong L, Yi R, Jingsheng L (2009) Realization and comparison of QRD algorithms for STAP. In: 2nd Asian-Pacific Conference on Synthetic Aperture Radar (APSAR, 2009), 306–309.
  30. 30.
    Bi F-K, Zhang D-Y, Cai X-C, Li L, Liu Y-X (2014) Fast reduced-rank STAP algorithm based on Gram-Schmidt orthogonalisation for airborne radar. Int J Electron. Google Scholar
  31. 31.
    Chang RC-H, Lin C-H, Lin K-H, Huang C-L, Chen F-C (2010) Iterative QR decomposition architecture using the modified Gram-Schmidt algorithm for MIMO systems. IEEE Trans Circuits Syst I Regul Pap 57(5):1095–1102. MathSciNetCrossRefGoogle Scholar

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Authors and Affiliations

  1. 1.Department of Electrical and Computer Engineering, Science and Research BranchIslamic Azad UniversityTehranIran
  2. 2.Department of Electrical EngineeringUniversity of GuilanRashtIran
  3. 3.Department of Electrical Engineering, Yadegar-e-Emam BranchIslamic Azad UniversityTehranIran

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