A joint optimization method for NoC topology generation

  • Yonghui Li
  • Kun Wang
  • Huaxi Gu
  • Yintang Yang
  • Nan Su
  • Yawen Chen
  • Haibo Zhang
Article
  • 26 Downloads

Abstract

The increasing demand on efficient intra-chip communication of multicore systems has driven the interconnection structure to evolve from bus/ring to Network-on-Chip (NoC). NoC design is fundamentally based on network topology generation and floorplanning. This paper proposes a joint optimization method to generate network topologies based on the floorplanning of heterogeneous IP cores for a given application-specific NoC. This method starts with clustering the heterogeneous IP cores according to their communication workloads using fuzzy clustering. It proceeds to apply a genetic algorithm to optimize the floorplanning by minimizing power consumption and/or chip area. By adding a router to each cluster of IP cores, network topologies are further generated via connecting routers based on the principles of scale-free networks. Experiments with a video processing application show that the optimized floorplanning of IP cores can be achieved by either minimizing the power consumption or chip area. An OPNET simulator is used to evaluate the performance of the NoC designed based on the proposed method. Experimental results demonstrate that the performance requirements of the application-specific NoC can be satisfied.

Keywords

Application-specific Network-on-Chip Floorplanning Topology generation Optimization 

Notes

Acknowledgements

This work was supported by the National Science Foundation of China under Grants 61634004, and Grant 61472300, the Fundamental Research Funds for the Central Universities Grant No. JB180309 and No. JB170107, and the key research and development plan of Shaanxi province No. 2017ZDCXL-GY-05-01.

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Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  1. 1.State Key Laboratory of ISNXidian UniversityXi’anChina
  2. 2.School of Computer ScienceXidian UniversityXi’anChina
  3. 3.Institute of MicroelectronicsXidian UniversityXi’anChina
  4. 4.Department of Computer ScienceUniversity of OtagoDunedinNew Zealand

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