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The Journal of Supercomputing

, Volume 74, Issue 7, pp 2905–2915 | Cite as

A highly efficient dynamic router for application-oriented network on chip

  • Nan Su
  • Huaxi Gu
  • Kun Wang
  • Xiaoshan Yu
  • Bowen Zhang
Article
  • 129 Downloads

Abstract

With the number of processor cores increasing in chip multiprocessors, the network on chip becomes a reliable structure with its perfect parallel communication performance. The traditional static router suffers a bad performance because of low buffer utilization for application-oriented network on chip. In this paper, a dynamic router which can take into account the unbalanced traffic for application-oriented network on chip is proposed. The router combines the inter-port and intra-port buffer allocation mechanism, which makes efficient use of buffer resources and avoids the head of line blocking. Furthermore, the proposed router can solve the problem of unbalanced load effectively between different ports on the same router. Simulation results show that the on-chip routers balance traffic between ports and increase the buffer utilization by 21.8%, thus optimizing delay and throughput performance for application-oriented network on chip.

Keywords

Network on chip Router Buffer allocation 

Notes

Acknowledgements

This work was supported by the National Science Foundation of China under Grants 61634004, and Grant 61472300, the Fundamental Research Funds for the Central Universities Grant No. JB180309 and No. JB170107, and the key research and development plan of Shaanxi province No. 2017ZDCXL-GY-05-01.

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Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  1. 1.State Key Laboratory of ISNXidian UniversityXi’anChina
  2. 2.School of Computer ScienceXidian UniversityXi’anChina

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