The Journal of Supercomputing

, Volume 74, Issue 7, pp 2905–2915 | Cite as

A highly efficient dynamic router for application-oriented network on chip

  • Nan Su
  • Huaxi Gu
  • Kun Wang
  • Xiaoshan Yu
  • Bowen Zhang


With the number of processor cores increasing in chip multiprocessors, the network on chip becomes a reliable structure with its perfect parallel communication performance. The traditional static router suffers a bad performance because of low buffer utilization for application-oriented network on chip. In this paper, a dynamic router which can take into account the unbalanced traffic for application-oriented network on chip is proposed. The router combines the inter-port and intra-port buffer allocation mechanism, which makes efficient use of buffer resources and avoids the head of line blocking. Furthermore, the proposed router can solve the problem of unbalanced load effectively between different ports on the same router. Simulation results show that the on-chip routers balance traffic between ports and increase the buffer utilization by 21.8%, thus optimizing delay and throughput performance for application-oriented network on chip.


Network on chip Router Buffer allocation 



This work was supported by the National Science Foundation of China under Grants 61634004, and Grant 61472300, the Fundamental Research Funds for the Central Universities Grant No. JB180309 and No. JB170107, and the key research and development plan of Shaanxi province No. 2017ZDCXL-GY-05-01.


  1. 1.
    Das S, Doppa JR, Pande PP, et al. (2016) Energy-efficient and reliable 3D network-on-chip (NoC): architectures and optimization algorithms. In: International Conference on Computer-Aided DesignGoogle Scholar
  2. 2.
    Benini L, Micheli GD (2002) Networks on chips: a New SoC paradigm. IEEE Comput 35(1):70–78CrossRefGoogle Scholar
  3. 3.
    Sharma V, Agarwal R, Gaur MS et al. (2010) ERA: an efficient routing algorithm for power throughput and latency in network-on-chip. In: Journal of Lecture Notes in Computer Science. pp 481–490Google Scholar
  4. 4.
    Rahmani AM, Latif K, Liljeberg P, Plosila J, Tenhunen H (2011) A stacked mesh 3D NoC architecture enabling congestion-aware and reliable inter-layer communication. In: Proceedings of International Euromicro Conference on Parallel, Distributed and Network-Based Processing. pp 423–430Google Scholar
  5. 5.
    Bhandarkar SM, Arabnia HR (1995) The REFINE multiprocessor: theoretical properties and algorithms. Parallel Comput 21(11):1783–1806CrossRefGoogle Scholar
  6. 6.
    Arabnia HR, Smith JW (1993) A reconfigurable interconnection network for imaging operations and its implementation using a multi-stage switching box. In: Proceedings of the 7th Annual International High Performance Computing Conference. The 1993 High Performance Computing: New Horizons Supercomputing Symposium, Calgary, Alberta, Canada, June. pp 349–357Google Scholar
  7. 7.
    Arif Wani M, Arabnia HR (2003) Parallel edge-region-based segmentation algorithm targeted at reconfigurable multi-ring network. J Supercomput 25(1):43–63CrossRefzbMATHGoogle Scholar
  8. 8.
    Arabnia HR (1990) A parallel algorithm for the arbitrary rotation of digitized images using process-and-data-decomposition approach. J Parallel Distrib Comput 10(2):188–193CrossRefGoogle Scholar
  9. 9.
    Bhandarkar SM, Arabnia HR (1995) The hough transform on a reconfigurable multi-ring network. J Parallel Distrib Comput 24(1):107–114CrossRefGoogle Scholar
  10. 10.
    Arabnia HR (1996) Distributed stereocorrelation algorithm. In: International Journal of Computer Communications. pp 707–712Google Scholar
  11. 11.
    Cheng B, Fan J, Jia X et al (2013) Parallel construction of independent spanning trees and an application in diagnosis on Möbius cubes. J Supercomput 65(3):1279–1301CrossRefGoogle Scholar
  12. 12.
    Liu Zhao, Fan Jianxi, Jia Xiaohua (2015) Embedding complete binary trees into parity cubes. J Supercomput 71(1):1–27CrossRefGoogle Scholar
  13. 13.
    Yu Zhigang, Wang Xinyu, Shen Kele (2016) Conditional forwarding: simple flow control to increase adaptivity for fully adaptive routing algorithms. J Supercomput 72(2):639–653CrossRefGoogle Scholar
  14. 14.
    Rahmani A, Latif K (2012) ARB-NET: a novel adaptive monitoring platform for stacked mesh 3D NoC architectures. In: Proceedings of International Asia and South Pacific Conference on Design Automation (ASP-DAC). pp 413–418Google Scholar
  15. 15.
    Noghondar, Fadakar Amir, Reshadi Midia (2015) A low-cost and latency bypass channel-based on-chip network. J Supercomput 71(10):3770–3786CrossRefGoogle Scholar
  16. 16.
    Touzene Abderezak, Day Khaled (2015) All-to-all broadcasting in torus Network on chip. J Supercomput 71(7):2585–2596CrossRefGoogle Scholar
  17. 17.
    Onizawa N, Matsumoto A, Funazaki T et al (2014) High-throughput compact delay-insensitive asynchronous noc router. IEEE Trans Comput 63(3):637–649MathSciNetCrossRefzbMATHGoogle Scholar
  18. 18.
    Xin L, Choy CS (2012) A low-latency NoC router with lookahead bypass. In: IEEE International Symposium on Circuits and SystemsGoogle Scholar
  19. 19.
    Wang C et al (2013) Scalable load balancing congestion-aware Network-on-Chip router architecture. J Comput Syst Sci 79:421–439MathSciNetCrossRefzbMATHGoogle Scholar
  20. 20.
    Dally WJ (1990) Virtual-channel flow control. In: International Symposium on Computer Architecture (ISCA)Google Scholar
  21. 21.
    Evripidou M, Nicopoulos C, Soteriou V, et al. (2012) Virtualizing virtual channels for increased network-on-chip robustness and upgradeability. In: IEEE Computer Society Annual Symposium (VLSI)Google Scholar
  22. 22.
    Nicopoulos CA, Park D, Kim J, et al. (2006) ViChaR: a dynamic virtual channel regulator for network-on-chip routers. In: IEEE International Symposium on MicroarchitectureGoogle Scholar
  23. 23.
    Matos D, Concatto C, Kreutz M et al (2011) Reconfigurable routers for low power and high performance. IEEE Transactions on Very Large Scale Integration Systems 19(11):2045–2057CrossRefGoogle Scholar
  24. 24.
    Xu Y, Zhao B, Zhang Y, et al. (2010) Simple virtual channel allocation for high throughput and high frequency on-chip routers. In: International Symposium on High Performance Computer ArchitectureGoogle Scholar
  25. 25.
    Rahmani AM, Liljeberg P, Latif K et al. (2011) Congestion aware, fault tolerant, and thermally efficient inter-layer communication scheme for hybrid NoC-bus 3D architectures, NOCS. In: Fifth ACM/IEEE International Symposium on Networks-On-Chip, Pittsburgh, Pennsylvania. pp 65–72Google Scholar
  26. 26.
    Ben-Itzhak Y, Cidon I, Kolodny A et al (2015) Heterogeneous NoC router architecture. IEEE Trans Parallel Distrib Syst 26(9):2479–2492CrossRefGoogle Scholar
  27. 27.
    Jose J, Mahathi KV, Shankar JS, et al. (2012) TRACKER: a low overhead adaptive NoC router with load balancing selection strategy. In: IEEE/ACM International Conference on Computer-Aided DesignGoogle Scholar
  28. 28.
    Oveisgharan M, Khan GN (2015) Index-based round-robin arbiter for NoC routers. In: IEEE Computer Society Annual SymposiumGoogle Scholar
  29. 29.
    Tran AT, Baas BM (2014) Achieving high-performance on-chip networks with shared-buffer routers. IEEE Trans Very Large Scale Integr Syst 22(6):1391–1403CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  1. 1.State Key Laboratory of ISNXidian UniversityXi’anChina
  2. 2.School of Computer ScienceXidian UniversityXi’anChina

Personalised recommendations