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SpExSim: assessing kernel suitability for C-based high-level hardware synthesis

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We present SpExSim, a software tool for quickly surveying legacy code bases for kernels that could be accelerated by FPGA-based compute units. We specifically aim for low development effort by considering the use of C-based high-level hardware synthesis, instead of complex manual hardware designs. SpExSim not only exploits the spatially distributed model of computation commonly used on FPGAs, but can also model the effect of two different microarchitectures commonly used in C-to-hardware compilers, including pipelined architectures with modulo scheduling. The estimations have been validated against actual hardware generated by two current HLS tools.

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  2. \(\text {Spatial factor}=\frac{\text {Exec.-Time (Sequential)}}{\text {Exec.-Time (Blockwise)}}\).

  3. \(\text {Pipeline factor}=\frac{\text {Exec.-Time (Blockwise)}}{\text {Exec.-Time (Pipeline)}}\).


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Correspondence to Julian Oppermann.

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This work was partially funded by the EU in the FP7 research project REPARA (ICT-609666).

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Oppermann, J., Sommer, L. & Koch, A. SpExSim: assessing kernel suitability for C-based high-level hardware synthesis. J Supercomput 75, 4062–4077 (2019).

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  • Reconfigurable computing
  • FPGA
  • Hardware acceleration
  • High-level synthesis
  • Estimation
  • Legacy code