The Journal of Supercomputing

, Volume 73, Issue 6, pp 2402–2429

Multi-cache resizing via greedy coordinate descent

Article

DOI: 10.1007/s11227-016-1927-0

Cite this article as:
Choi, I.S. & Yeung, D. J Supercomput (2017) 73: 2402. doi:10.1007/s11227-016-1927-0
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Abstract

To reduce power consumption in CPUs, researchers have studied dynamic cache resizing. However, existing techniques only resize a single cache within a uniprocessor or the shared last-level cache (LLC) within a multi-core CPU. To maximize benefits, it is necessary to resize all caches, which in today’s CPUs includes one or two private caches per core and a shared LLC. Such multi-cache resizing (MCR) is challenging, because the multiple resizing decisions are coupled, yielding an enormous configuration space. In this paper, we present a dynamic MCR technique that uses search-based optimization. Our main contribution is a set of heuristics that enable the search to find the best configuration rapidly. In particular, our search moves in a coordinate descent (Manhattan) fashion across the configuration space. At each search step, we select the next cache for resizing greedily based on a power efficiency gain metric. To further enhance search speed, we permit parallel greedy selection. Across 60 multi-programmed workloads, our technique reduces power by 13.9% while sacrificing 1.5% of the performance.

Keywords

Cache resizing Multi-core CPUs Search-based optimization Power-efficient computing 

Funding information

Funder NameGrant NumberFunding Note
National Science Foundation
  • CCF-1117042
Defense Advanced Research Projects Agency
  • HR0011-13-2-0005

Copyright information

© Springer Science+Business Media New York 2016

Authors and Affiliations

  1. 1.SamsungSan JoseUSA
  2. 2.University of Maryland at College ParkCollege ParkUSA

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