The Journal of Supercomputing

, Volume 73, Issue 5, pp 2187–2213 | Cite as

Mapping multiple applications onto 3D NoC-based MPSoCs supporting wireless links



Three-dimensional integrated circuits (3D ICs) are suitable alternatives to traditional two-dimensional (2D) ICs by leveraging its advantage of better performance and packaging; therefore, they have been highly considered by researchers. On the other hand, emerging network-on-chip (NoC) based many-core chips provides great potential for running multiple applications simultaneously. However, using this approach leads to the increase of the interference between applications, resulting in lowering the performance of each application. Hence, mapping tasks belonging to various applications onto the nodes of an architecture is a very important issue. In this study, based on partitioning concept, a novel methodology for mapping of multiple applications at run-time onto an irregular wireless 3D NoC-based multiprocessor system-on-chip (MPSoC) platform in which more than one task can be supported by each processing element (PE) was presented. In the second algorithm (enhanced irregular-partitioning best neighbor), according to the number of applications running simultaneously, the partitioning of network will be dynamically changed to minimize the communication overhead and congestion on the NoC that leads to more efficient task mapping. The simulation results reveal that the second proposed algorithm (enhanced IPBN) in comparison with NPBN (non-partitioning best neighbor) algorithm and our first proposed algorithm (basic IPBN) enhances the performance by decreasing the total execution time, average hop count, average channel load and energy consumption.


Irregular wireless 3D network-on-chip Multiprocessor system-on-chip (MPSoC) Heterogeneous architecture Application Partitioning Dynamic task mapping 


  1. 1.
    Bjerregaard T, Mahadevan S (2006) A survey of research and practices of network-on-chip. ACM Comput Surv (CSUR) 38:1–51CrossRefGoogle Scholar
  2. 2.
    Lee J, Zhu M, Choi K, Ho AJ, Sharma R (2011) 3D network-on-chip with wireless links through inductive coupling. In: SoC Design Conference (ISOCC), 2011 International, pp 353–356Google Scholar
  3. 3.
    Kumar Singh A, Srikanthan T, Kumar A, Jigang W (2010) Communication-aware heuristics for run-time task mapping on NoC-based MPSoC platforms MPSoC platforms. J Syst Archit 56(7):242–255Google Scholar
  4. 4.
    Seiculescu C, Murali S, Benini L, De Micheli G (2010) SunFloor 3D: a tool for networks on Chip Topology Synthesis for 3-D Systems on Chips. IEEE Trans Comp 29(12):1987–2000Google Scholar
  5. 5.
    Take Y, Matsutani H, Sasaki D, Koibuchi M, Kuroda T, Amano H (2014) 3D NoC with inductive-coupling links for building-block SiPs. IEEE Trans Comp 63(3):748–763Google Scholar
  6. 6.
    Feero BS, Pande PP (2009) Networks-on-chip in a three-dimensional environment: a performance evaluation. IEEE Trans Comp 58(1):32–45Google Scholar
  7. 7.
    Zhang Z, Yin S, Liu L, Wei S (2013) An inductive-coupling interconnected application-specific 3D NoC design. In: Circuits and Systems (ISCAS), IEEE International Symposium on, pp 550–553Google Scholar
  8. 8.
    Matsutani H, Bogdan P, Marculescu R, Take Y, Sasaki D, Zhang H, Koibuchi M, Kuroda T, Amano H (2013) A case for wireless 3D NoCs for CMPs. In: Design Automation Conference (ASP-DAC), 2013 18th Asia and South Pacific, pp 23–28Google Scholar
  9. 9.
    Matsutani H, Koibuchi M, Fujiwara I, Kagami T, Take, Y, Kuroda T, Bogdan P, Marculescu R, Amano H (2014) Low-latency wireless 3D NoCs via randomized shortcut chips. In: Design, Automation and Test in Europe Conference and Exhibition (DATE), pp 1–6Google Scholar
  10. 10.
    Lysne O, Skeie T, Reinemo S-A, Theiss I (Jan. 2006) Layered routing in irregular networks. In: Parallel and Distributed Systems, IEEE Transactions on, pp 51–65Google Scholar
  11. 11.
    Solheim AG, Lysne O, Skeie T, Sodring T, Theiss I (2006) Routing for the asi fabric manager. Commun Mag IEEE 44:39–44CrossRefGoogle Scholar
  12. 12.
    Wettin P, Murray J, Kim R, Xinmin Yu, Pande PP, Heo D (2014) Performance evaluation of wireless NoCs in presence of irregular network routing strategies. In: Design, Automation and Test in Europe Conference and Exhibition (DATE), pp 1–6Google Scholar
  13. 13.
    Jang W, Pan DZ (2010) A3MAP: architecture-aware analytic mapping for networks-on-chip. In: Design Automation Conference (ASP-DAC), 2010 15th Asia and South Pacific, pp 523–528Google Scholar
  14. 14.
    Huang J, Buckl C, Raabe A, Knoll A (2011) Energy-aware task allocation for network-on-chip based heterogeneous multiprocessor systems. In: Parallel, Distributed and Network-Based Processing (PDP), 2011 19th Euromicro International Conference on, pp 447–454Google Scholar
  15. 15.
    Manolache S, Eles P, Peng Z (2005) Fault and energy-aware communication mapping with guaranteed latency for applications implemented on NoC. In: Design Automation Conference, Proceedings, 42nd, pp 266–269Google Scholar
  16. 16.
    Bolanos F, Rivera F, Aedo JE, Bagherzadeh N (2013) From UML specifications to mapping and scheduling of tasks into a NoC, with reliability considerations. J Syst Archit 59:429–440CrossRefGoogle Scholar
  17. 17.
    Mandelli M, Ost L, Carana E, Guindani G, Gouvea T, Medeiros M, Moraes FG (2011) Energy- aware dynamic task mapping for NoC-based MPSoCs. In: ISCAS, IEEE, pp 1676–1679Google Scholar
  18. 18.
    Carvalho E, Calazans N, Moraes F (2010) Dynamic task Mapping for MPSoCs. Des Test Comput IEEE 27:26–35CrossRefGoogle Scholar
  19. 19.
    Yang B, Guang L, Santti T, Plosila J (2013) Mapping multiple applications with unbounded and bounded number of cores on many-core networks-on-chip. Microprocess Microsyst 37:460–471CrossRefGoogle Scholar
  20. 20.
    Haoyuan Y, Thomas H, Klaus H (2013) Fast and optimized task allocation method for low vertical link density 3-dimensional networks-on-Chip based many core systems. In: Design, Automation & Test in Europe Conference & Exhibition (DATE), pp 1777–1782Google Scholar
  21. 21.
    Carvalho E, Marcon C, Calazans N, Moraes F (2009) Evaluation of static and dynamic task mapping algorithms in NoC-based MPSoC. In: System-on-Chip, International Symposium on, pp 087–090Google Scholar
  22. 22.
    Carvalho E, Moraes F (2008) Congestion-aware task mapping in heterogeneous MPSoCs. In: System-on-Chip, International Symposium on, pp 1–4Google Scholar
  23. 23.
    Arabnia HR, Oliver MA (1986) Fast operations on raster images with SIMD machine architectures. Int J Eurographics Assoc (Computer Graphics Forum) 5(3):179–188CrossRefGoogle Scholar
  24. 24.
    Arabnia HR, Oliver MA (1987) A transputer network for the arbitrary rotation of digitised images. Comput J 30(5):425–433CrossRefGoogle Scholar
  25. 25.
    Arabnia HR, Oliver MA (1987) Arbitrary rotation of raster images with SIMD machine architectures. Int J Eurographics Assoc (Computer Graphics Forum) 6(1):3–12CrossRefGoogle Scholar
  26. 26.
    Arabnia HR, Oliver Martin A (1989) A transputer network for fast operations on digitised images. Int J Eurographics Assoc (Computer Graphics Forum) 8(1):3–12CrossRefGoogle Scholar
  27. 27.
    Arabnia HR (1990) A parallel algorithm for the arbitrary rotation of digitized images using process-and-data-decomposition approach. J Parallel Distrib Comput 10(2):188–193CrossRefGoogle Scholar
  28. 28.
    Arabnia HR, Smith JW (1993) A reconfigurable interconnection network for imaging operations and its implementation using a multi-stage switching box. In: Proceedings of the 7th Annual International High Performance Computing Conference. The 1993 High Performance Computing: New Horizons SuperComputing Symposium, Calgary, Alberta, Canada, June, pp 349–357Google Scholar
  29. 29.
    Chen T, Fu W, Xie B, Wang C (2014) Packet triggered prediction based task migration for network- on-chip. In: Euromicro Conference on Parallel, Distributed and Network-Based Processing, pp 316–324Google Scholar
  30. 30.
    Ben Achballah A, Ben Saoud S (2013) A survey of network-on-chip tools. Int J Adv Comput Sci Appl (IJACSA) 4(9):61–67Google Scholar
  31. 31.
    Ebrahimi M, Daneshtalab M, Liljeberg P, Plosila J, Tenhunen H (2013) Cluster-based topologies for 3D Networks-on-chip using advanced inter-layer bus architecture. JCSS CADS 2010:475–491MathSciNetMATHGoogle Scholar
  32. 32.
    Canhao XuT, Schley G, Liljeberg P, Radetzki M, Plosila J (2013) Optimal placement of vertical connections in 3D network-on-chip. J Syst Archit 59:441–454CrossRefGoogle Scholar
  33. 33.
    Miller F, Wild T, Herkersdorf A (2013) Virtualized and fault-tolerant inter-layer-links for 3D-ICs. Microprocess Microsyst 37(8):823–835Google Scholar
  34. 34.
    Pande PP, Grecu C, Jones M, Ivanov A, Saleh R (Aug. 2005) Performance evaluation and design trade-offs for network-on-chip interconnect architectures. Comput IEEE Trans 54(8):1025–1040Google Scholar
  35. 35.
    Wang S, Jin T (2014) Wireless network-on-chip: a survey. J Eng 1–7. doi: 10.1049/joe.2013.0209
  36. 36.
    Feng Q, Ban D, Li H, Han G, Dou W (Augus.2012) Performance analysis of wireless 3D network on chip. In: Instrumentation & Measurement, Sensor Network and Automation (IMSNA), 2012 International Symposium on, pp 232–235Google Scholar
  37. 37.
    Kahng AB, Li B, Peh Li-Shiuan, Samadi K (2012) ORION 2.0: a power-area simulator for interconnection networks. IEEE Trans Very Large Scale Integr (VLSI) Syst 20(1):191–196CrossRefGoogle Scholar
  38. 38.
    Hu J, Marculescu R (Jan. 2003) Energy-aware mapping for tile-based NoC architectures under performance constraints. In: Design Automation Conference. Proceedings of the ASP-DAC 2003. Asia and South Pacific, pp 233–239Google Scholar
  39. 39.
    Arabnia HR (1995) A distributed stereocorrelation algorithm. In: Proceedings of Computer Communications and Networks (ICCCN’95), IEEE, pp 479–482Google Scholar
  40. 40.
    Bhandarkar SM, Arabnia HR, Smith JW (1995) A reconfigurable architecture for image processing and computer vision. Int J Pattern Recognit Artif Intelli (IJPRAI) (special issue on VLSI Algorithms and Architectures for Computer Vision, Image Processing, Pattern Recognition And AI) 9(2):201–229Google Scholar
  41. 41.
    Bhandarkar SM, Arabnia HR (1995) The Hough transform on a reconfigurable multi-ring network. J Parallel Distrib Comput 24(1):107–114CrossRefGoogle Scholar
  42. 42.
    Bhandarkar SM, Arabnia HR (1995) The REFINE multiprocessor: theoretical properties and algorithms. Parallel Comput (Journal) Elsevier 21(11):1783–1806CrossRefGoogle Scholar
  43. 43.
    Arabnia HR, Bhandarkar SM (1996) Parallel stereocorrelation on a reconfigurable multi-ring network. J Supercomput (Springer Publishers) 10(3):243–270CrossRefMATHGoogle Scholar
  44. 44.
    Wani MA, Arabnia HR (2003) Parallel edge-region-based segmentation algorithm targeted at reconfigurable multi-ring network. J Supercomput 25(1):43–63CrossRefMATHGoogle Scholar
  45. 45.
    Thapliyal, H, Arabnia HR, Vinod AP (2006) Combined integer and floating point multiplication architecture (CIFM) for FPGAs and its reversible logic implementation. In: 49th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS’06),San Juan, Puerto Rico, August 6–9, pp 148–154Google Scholar
  46. 46.
    Thapliyal, H, Arabnia HR (2006) Reversible programmable logic array (RPLA) using Fredkin and Feynman gates for industrial electronics and applications. In: Proceedings of the 2006 International Conference on Computer Design & Conference on Computing in Nanotechnology (CDES’06: June 26–29, 2016; Las Vegas, USA), pp 70–74Google Scholar
  47. 47.
    Vallerio K (2008) Manual task graphs for free (TGFF v3.0)Google Scholar
  48. 48.
    Access Noxim website (2015) Accessed 3 Jan 2015

Copyright information

© Springer Science+Business Media New York 2016

Authors and Affiliations

  1. 1.Department of Computer Engineering, Science and Research BranchIslamic Azad UniversityTehranIran

Personalised recommendations