The Journal of Supercomputing

, Volume 73, Issue 5, pp 1733–1759 | Cite as

Automatic synthesis of quaternary quantum circuits

  • Mozammel H. A. Khan
  • Himanshu Thapliyal
  • Edgard Munoz-Coreas


Quaternary encoded binary circuits are more compact than their binary counterpart. Although quaternary reversible circuits are realizable, design of such circuits is still in its infancy. This work proposes a new, enhanced method of quaternary Galois field sum of products (QGFSOP) synthesis for quaternary quantum circuits. To reduce QGFSOP product terms, the algorithm makes use of 11 newly defined quaternary Galois field (QGF) expansions (for a total of 21 QGF expansions). This algorithm achieves QGFSOP minimization with the assistance of a pseudo-Kronecker Galois field decision diagram (QGFDD). This is a novel approach for QGFSOP synthesis. Finally, QGFSOP expressions are translated into quantum cost optimized quaternary quantum circuits using: (1) newly developed quaternary quantum gate realizations of controlled Feynman and Toffoli gate that are optimized in terms of quantum cost, (2) use of composite literals consisting of 1 digit and M–S gates. Performance evaluation against existing works in the literature determined that our proposed method achieves an average QGFSOP expression product term savings of 32.66 %. Also, the synthesized QGFSOP circuits were evaluated in terms of quantum cost.


Quaternary Galois field decision diagram Quaternary Galois field sum of products minimization Quaternary reversible circuit design 


  1. 1.
    Frost-Murphy SE ,Ottavi M, Frank MP, DeBenedictis EP (2006) On the design of reversible qdca systems. Technical report, Sandia National LaboratoriesGoogle Scholar
  2. 2.
    Ren J, Semenov VK (2011) Progress with physically and logically reversible superconducting digital circuits. IEEE Trans Appl Supercond 21(3):780–786CrossRefGoogle Scholar
  3. 3.
    Vos AD, Rentergem YV (2005) Power consumption in reversible logic addressed by a ramp voltage. In: Proc. 15th Intl. Workshop on Power and Timing Modeling, Optimization and Simulation, Lecture Notes in Computer Science, vol 3728, pp 207–216Google Scholar
  4. 4.
    Nielsen M, Chuang I (2000) Quantum computation and quantum information. Cambridge University Press, CambridgeMATHGoogle Scholar
  5. 5.
    Wille R, Drechsler R (2009) BDD-based synthesis of reversible logic for large functions. In: Proc. 46th ACM/IEEE Design Automation Conf. (DAC ’09), pp 270–275Google Scholar
  6. 6.
    Mochizuki A, Shirahama H, Hanyu T (2014) Design of a quaternary single-ended current-mode circuit for an energy-efficient inter-chip asynchronous communication link. In: Proc. 44th IEEE International Symposium on Multiple-Valued Logic (ISMVL), pp 67–72Google Scholar
  7. 7.
    Onizawa N, Hanyu T, Gaudet VC (2009) High-throughput bit-serial LDPC decoder LSI based on multiple-valued asynchronous interleaving. IEICE Trans Electron E92–C(6):867–874CrossRefGoogle Scholar
  8. 8.
    Patel KSV, Gurumurthy KS (2010) Arithmetic operations in multi-valued logic. arXiv:1003.5442
  9. 9.
    Sasao T, Nakahara H, Matsuura M, Kawamura Y, Butler JT (2009) A quaternary decision diagram machine and the optimization of its code. In: 39th International Symposium on Multiple-Valued Logic (ISMVL 2009), pp 362–369Google Scholar
  10. 10.
    Okamoto K, Homma N, Aoki T (2014) Formal design of arithmetic circuits over galois fields based on normal basis representations. IEICE Trans 97–D(9):2270–2277CrossRefGoogle Scholar
  11. 11.
    Homma N, Saito K, Aoki T (2012) Formal design of multiple-valued arithmetic algorithms over Galois fields and its application to cryptographic processor. ISMVL, Victoria, pp 110–115Google Scholar
  12. 12.
    Feinstein DY, Thornton MA (2015) Quantum multiple-valued decision diagrams containing skipped variables. J Multi Valued Logic Soft Comput 24(1–4):93–108MathSciNetGoogle Scholar
  13. 13.
    Liang J, Chen L, Han J, Lombardi F (2014) Design and evaluation of multiple valued logic gates using pseudo N-type carbon nanotube FETs. IEEE Trans Nanotechnol 13(4):695–708CrossRefGoogle Scholar
  14. 14.
    Muthukrishnan A, Stroud CR Jr (2000) Multivalued logic gates for quantum computation. Phys Rev A 62(5):052309/1-8MathSciNetCrossRefGoogle Scholar
  15. 15.
    Meena JK, Lal C, Gupta H, Jain SC (2015) Low cost realization of square and square multiplication operations using toffoli gates. Green Computing and Internet of Things (ICGCIoT), International Conference on, Noida, pp 1304–1308Google Scholar
  16. 16.
    Khan MHA, Siddika NK, Perkowski MA (2008) Minimization of quaternary Galois field sum of products expression for multi-output quaternary logic function using quaternary Galois field decision diagram. In: Proc. Intl. Symp. Multiple-Valued Logic, pp 125–130Google Scholar
  17. 17.
    Mandal SB, Chakrabarti A, Sur-Kolay S (2012) A synthesis method for quaternary quantum logic circuits, in Progress in VLSI Design and Test. LNCS 7373:270–280Google Scholar
  18. 18.
    Khan MMM, Biswas AK, Chowdhury S, Tanzid M, Mohsin KM, Hasan M, Kahn AI (2008) Quantum realization of some quaternary circuits. In: Proc. 2008 IEEE Region 10 Conference, pp 1–5Google Scholar
  19. 19.
    Khan MHA (2007) Reversible realization of quaternary decoder, multiplexer, and demultiplexer circuits. Eng Lett 15(2):203–207Google Scholar
  20. 20.
    Yang S (2014) Logic synthesis and optimization benchmarks users guide version 3.0.;jsessionid=7D8CF3ACF680A3BD7D10E6CCA602CABA?doi= Accessed on 06 August 2014
  21. 21.
    Deb A, Das DK, Sur-Kolay S (2013) Modular design for symmetric functions using quantum quaternary logic. In: Proc. 5th Intl. Symp. Electronic System Design (ISED)Google Scholar
  22. 22.
    Meena JK, Jain SC, Gupta H, Gupta S (2015) Synthesis of balanced quaternary reversible logic circuit. In: Circuit, Power and Computing Technologies (ICCPCT), International Conference on, Nagercoil, pp 1–6Google Scholar
  23. 23.
    Khan MHA, Perkowski MA (2007) GF(4) based synthesis of quaternary reversible/quantum logic circuits. J Multiple Valued Logic Soft Comput 13:583–603MathSciNetMATHGoogle Scholar
  24. 24.
    Sarabi A, Ho PF, Iravani K, Daasch WR, Perkowski MA (1993) Minimal multi-level realization of switching functions based on Kronecker functional decision diagrams. In: Proc. IEEE Intl. Workshop Logic Synthesis, pp P3a-1-6Google Scholar
  25. 25.
    Khan MHA, Perkowski MA, Khan MR (2005) Ternary GFSOP minimization using Kronecker decision diagrams and their synthesis with quantum cascades. J Multi Valued Logic Soft Comput 11:567–602MATHGoogle Scholar
  26. 26.
    Jayashree H, Thapliyal H, Arabnia HR, Agrawal V (2016) Ancilla-input and garbage-output optimized design of a reversible quantum integer multiplier. J Supercomput 72(4):1477–1493CrossRefGoogle Scholar
  27. 27.
    Thapliyal H, Jayashree HV, Nagamani AN, Arabnia HR (2013) Progress in reversible processor design: a novel methodology for reversible carry look-ahead adder. Springer Trans Comput Sci 7420:73–97Google Scholar
  28. 28.
    Thapliyal H, Arabnia HR, Srinivas MB (2009) Efficient reversible logic design of BCD subtractors. In: Springer Transactions on Computational Sciences Journal, LNCS 5300, vol 3, pp 99–121Google Scholar
  29. 29.
    Bocharov A, Roetteler M, Svore KM (2016) Factoring with Qutrits: Shor’s Algorithm on Ternary and Metaplectic Quantum Architectures. arXiv:1605.02756
  30. 30.
    Sharifi F, Moaiyeri MH, Navi K, Bagherzadeh N (2016) Ultra-low-power carbon nanotube FET-based quaternary logic gates, Taylor and Francis. Int J Electron 103(9):1524–1537Google Scholar
  31. 31.
    Sharifi F, Moaiyeri MH, Navi K, Bagherzadeh N (2015) Quaternary full adder cells based on carbon nanotube FETs. J Comput Electron 14(3):762–772CrossRefGoogle Scholar
  32. 32.
    Moaiyeri MH, Navi K, Hashemipour O (2012) Design and evaluation of CNFET-based quaternary circuits. Springer Circuits Syst Signal Process 31(5):1631–1652MathSciNetCrossRefGoogle Scholar
  33. 33.
    Kotiyal S, Thapliyal H, Ranganathan N (2010) Design of a ternary barrel shifter using multiple-valued reversible logic. In: Proceedings of the 10th IEEE International Conference on Nanotechnology (IEEE NANO). Seoul, Korea, pp 1104–1108Google Scholar

Copyright information

© Springer Science+Business Media New York 2016

Authors and Affiliations

  • Mozammel H. A. Khan
    • 1
  • Himanshu Thapliyal
    • 2
  • Edgard Munoz-Coreas
    • 2
  1. 1.Department of Computer Science and EngineeringEast West UniversityDhakaBangladesh
  2. 2.Department of Electrical and Computer EngineeringUniversity of KentuckyLexingtonUSA

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