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Application mapping onto mesh-based network-on-chip using constructive heuristic algorithms

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Abstract

Application mapping is an important part of network-on-chip (NoC) design, it tries to map the application onto a NoC-based platform. Because mapping an application onto the mesh architecture is NP-hard, there is no known algorithm for solving this problem in polynomial time. In this study, we propose a new application mapping algorithm for mapping an application onto the mesh topology NoC architecture to minimize the energy consumption. We compare the proposed algorithm with some previously proposed algorithm and exact mapping technique. Our experiments on multimedia benchmarks show that the proposed mapping algorithm obtains the same solutions as the optimal solutions that are generated by IPL on most of cases. On random benchmarks containing higher number of cores, we use less execution time to find better solution than CastNet and NMAP in large-scale mesh-based NoC.

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References

  1. Arabnia HR, Oliver MA (1989) A transputer network for fast operations on digitised images. Comput Graph Forum 8(1):3–12

    Article  Google Scholar 

  2. Bhandarkar SM, Arabnia HR (1995) The REFINE multiprocessor: theoretical properties and algorithms. Parallel Comput 21(11):1783–1806

    Article  Google Scholar 

  3. Darbari FM, Khademzadeh A, Fard GG (2009) CGMAP: a new approach to network-on-chip mapping problem. IEICE Electron Express 6(1):27–34

    Article  Google Scholar 

  4. Dick RP, Rhodes DL, Wolf W (1998) TGFF: task graphs for free. In: Proc. Int. Workshop Hardware/Software Codesign, pp 97–101

  5. Garey MR, Johnson DS (1979) Computers and intractability: a guide to the theory of NP-completeness. Freeman

  6. Hemani A, Jantsch A, Kumar S, Postula A, Oberg J, Millberg M, Lindqvist D (2000) Network on a chip: an architecture for billion transistor era. In: Proc. of the IEEE NorChip conference

  7. Hu J, Marculescu R (2005) Energy- and performance-aware mapping for regular NoC architectures. IEEE Trans Comput Aided Des Integr Circ Syst 24(4):551–562

    Article  Google Scholar 

  8. Leighton FT (1992) Introduction to parallel algorithms and architectures: arrays trees hypercubes. Morgan Kaufmann, San Mateo

    MATH  Google Scholar 

  9. Marculescu R, Ogras UY, Peh LS, Jerger NE, Hoskote Y (2009) Outstanding research problems in NoC design: systems, microarchitecture, and circuit perspectives. IEEE Trans Comput Aided Des Integr Circ Syst 28(1):3–21

    Article  Google Scholar 

  10. Murali S, De Micheli G (2004) Bandwidth constrained mapping of cores onto NoC architectures. In: Proceedings of design, automation and test in europe conference and exhibition (DATE), vol 2, pp 896–901

  11. Sahni S, Gonzalez T (1976) P-complete approximation problems. J Assoc Comput Mach 23(3):555–565

    Article  MathSciNet  MATH  Google Scholar 

  12. Sahu PK, Chattopadhyay S (2013) A survey on application mapping strategies for network-on-chip design. J Syst Archit 59(1):60–76

    Article  MathSciNet  Google Scholar 

  13. Sahu PK, Shah T, Manna K, Chattopadhyay S (2014) Application mapping onto mesh based network-on-chip using discrete particle swarm optimization. IEEE Trans Very Large Scale Integr (VLSI) Syst 22(2):300–312

    Article  Google Scholar 

  14. Sahu PK, Venkatesh P, Gollapalli S, Chattopadhyay S (2011) Application mapping onto mesh structured network-on-chip using particle swarm optimization. In: IEEE computer society annual symposium on VLSI, pp 335–336

  15. Shen T, Chao CH, Lien YK, Wu AY (2007) A new binomial mapping and optimization algorithm for reduced-complexity mesh-based on-chip network. In: Proceedings of NOCS07, pp. 317–322

  16. Tavanpour M, Khademzadeh A, Pourkiani S, Yaghobi M (2010) GBMAP: an evolutionary approach to mapping cores onto a mesh-based NoC architecture. J Commun Comput 7(3):1–7

    Google Scholar 

  17. Tosun S, Ozturk O, Ozen M (2009) An ILP formulation for application mapping onto network-on-chips. In: International conference on application of information and communication technologies (AICT), pp 1–5

  18. Tosun S, Ozturk O, Ozen M (2015) Application mapping algorithms for mesh-based network-on-chip architectures. J Supercomput 71(3):995–1017

    Article  Google Scholar 

  19. Tosun S (2011) New heuristic algorithm for energy aware application mapping and routing on mesh-based NoCs. J Syst Archit 57(1):69–78

    Article  Google Scholar 

  20. Tosun S (2011) Clustered-based application mapping method for network-on-chip. Adv Eng Softw 42(10):868–874

    Article  Google Scholar 

  21. Zhou L, Jing M, Yu Z, Zeng X (2012) Task-binding based branch-and-bound algorithm for NoC mapping. In: Circuits and systems (ISCAS), 2012 IEEE international symposium on. (ISCAS’12), pp 648–651

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Authors and Affiliations

  1. Department of Electronic and Computer Engineering, National Taiwan University of Science and Technology, Taipei, 106, Taiwan

    Chi-Hsiang Cheng & Wei-Mei Chen

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  1. Chi-Hsiang Cheng
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  2. Wei-Mei Chen
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Correspondence to Wei-Mei Chen.

Additional information

This work is partially supported by Ministry of Science Technology under the Grant MOST 104-2221-E-011-024.

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Cheng, CH., Chen, WM. Application mapping onto mesh-based network-on-chip using constructive heuristic algorithms. J Supercomput 72, 4365–4378 (2016). https://doi.org/10.1007/s11227-016-1746-3

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  • DOI: https://doi.org/10.1007/s11227-016-1746-3

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