The Journal of Supercomputing

, Volume 71, Issue 12, pp 4446–4475 | Cite as

Hybrid silicon-photonic network-on-chip for future generations of high-performance many-core systems

Article

Abstract

Photonic networks-on-chip (PNoCs) promise significant advantages over their electronic counterparts. In particular, they offer a potentially disruptive technology solution with fundamentally low power dissipation that remains independent of capacity while providing ultra-high throughput and minimal access latency. In conventional hybrid-PNoC systems, several electrical control functions, such as path setup, acknowledgment and Tear-down are necessary for the end-to-end optical transfer. However, the circuit-switched nature of photonic interconnect directly affects the performance and power characteristics of on-chip communication. In this paper, we propose an energy-efficient and high-throughput hybrid silicon-photonic network-on-chip, named PHENIC, targeted for future generations of high-performance many-core systems. PHENIC is based on a smart contention-aware path-configuration algorithm and an energy-efficient non-blocking optical switch to further exploit the low energy proprieties of the PNoC systems. Through detailed simulation, we demonstrate that the proposed system has a better performance and low energy dissipation compared to conventional hybrid-PNoCs.

Keywords

Hybrid silicon-photonic NoC Energy-efficient Non-blocking photonic switch Contention-aware Path configuration 

References

  1. 1.
    Ben Abdallah A (2013) Multicore systems-on-chip: practical hardware/software design, 2nd edn. Atlantis, Paris. ISBN-13: 978-9491216916. http://www.amazon.com/gp/product/9462390509?keywords=ben%20abdallah
  2. 2.
    Bhandarkar SM, Arabnia HR (1995) The REFINE multiprocessor: theoretical properties and algorithms. Parallel Comput (J) 21(11):1783–1806 (Elsevier)Google Scholar
  3. 3.
    Arabnia HR (1995) A distributed stereocorrelation algorithm. In: IEEE proceedings of computer communications and networks (ICCCN’95), pp 479–482Google Scholar
  4. 4.
    Arabnia HR, Hough MA (1989) A transputer network for fast operations on digitised images. Int J Eurograph Assoc (Comput Graph Forum) 8(1):3–12CrossRefGoogle Scholar
  5. 5.
    Arabnia HR, Oliver MA (1987) Arbitrary rotation of raster images with SIMD machine architectures. Int J Eurograph Assoc (Comput Graph Forum) 6(1):3–12CrossRefGoogle Scholar
  6. 6.
    Bhandarkar SM, Arabnia HR, Smith JW (1995) A reconfigurable architecture for image processing and computer vision. Int J Pattern Recognit Artif Intell (IJPRAI) (Spec Issue VLSI Algorithms Archit Comput Vis Image Process Pattern Recognit AI) 9(2):201–229Google Scholar
  7. 7.
    Arabnia HR, Bhandarkar SM (1996) Parallel stereocorrelation on a reconfigurable multi-ring network. J Supercomput 10(3):243–270 (Springer Publishers)MATHCrossRefGoogle Scholar
  8. 8.
    Bhandarkar SM, Arabnia HR (1995) The Hough transform on a reconfigurable multi-ring network. J Parallel Distrib Comput 24(1):107–114CrossRefGoogle Scholar
  9. 9.
    Arabnia HR, Oliver MA (1987) A transputer network for the arbitrary rotation of digitised images. Comput J 30(5):425–433CrossRefGoogle Scholar
  10. 10.
    Arabnia HR, Smith JW (1993) A reconfigurable interconnection network for imaging operations and its implementation using a multi-stage switching box. In: Proceedings of the 7th annual international high performance computing conference. The 1993 high performance computing: new horizons supercomputing symposium, Calgary, pp 349–357Google Scholar
  11. 11.
    Arabnia HR (1990) A parallel algorithm for the arbitrary of digitized images using process-and-data-decomposition approach. J Parallel Distrib Comput 10(2):188–193CrossRefGoogle Scholar
  12. 12.
    Arif Wani M, Arabnia HR (2003) Parallel edge-region-based segmentation algorithm targeted at reconfigurable multi-ring network. J Supercomput 25(1):43–63MATHCrossRefGoogle Scholar
  13. 13.
    Ben Ahmed A., Ben Abdallah A (2013) PHENIC: towards photonic 3D-network-on-chip architecture for high-throughput many-core systems-on-chip. In: Proceedings of the 14th international conference on sciences and techniques of automatic control and computer engineering, pp 1–9Google Scholar
  14. 14.
    Ben Ahmed A, Okuyama Y, Ben Abdallah A (2015) Contention-free routing for hybrid photonic mesh-based network-on-chip systems. In: Proceedings of the IEEE 9th international symposium on embedded multicore/many-core systems-on-chip (MCSoC-15)Google Scholar
  15. 15.
    Ben Ahmed A, Meyer M, Okuyama Y, Ben Abdallah A (2015) Hybrid photonic NoC based on non-blocking photonic switch and light-weight electronic router. In: The IEEE int. conf. on systems, man, and cybernetics (SMC-15)Google Scholar
  16. 16.
    Ben Ahmed A, Okuyama Y, Ben Abdallah A (2015) Non-blocking electro-optic network-on-chip router for high-throughput and low-power many-core systems. In: Proceedings of the IEEE world congress on information technology and computer applications (WCITCA’15)Google Scholar
  17. 17.
    Ben Ahmed A, Meyer M, Okuyama Y, Ben Abdallah A (2015) Efficient router architecture, design and performance exploration for many-core hybrid photonic network-on-chip (2D-PHENIC). In: Proceedings of the int. conf. on information science and control engineering (ICISCE), pp 202–206Google Scholar
  18. 18.
    Chen Z, Gu H, Chen Y, Chen Y, Zhang H (2013) Source-and destination-based wavelength assignment in optical network-on-chip: design and performance. In: Proceeding of the IEEE region 10 (TENCON’13), pp 1–4Google Scholar
  19. 19.
    Benini L, De Micheli G (2006) Networks on chips: technology and tools. Morgan Kauffmann, San Mateo. ISBN-13: 978-0123705211Google Scholar
  20. 20.
    Mori K, Esch A, Ben Abdallah A, Kuroda K (2010) Advanced design issues for OASIS network-on-chip architecture. In: Proceedings of the IEEE 5th international conference on broadband, wireless computing, communication and applications, pp 74–79Google Scholar
  21. 21.
    Ben Abdallah A, Sowa M (2006) Basic network-on-chip interconnection for future gigascale MCSoCs applications, communication and computation orthogonalization. In: Proceeding of the symposium on science, society, and technology, pp 4–6Google Scholar
  22. 22.
    Zhang L, Tan X, Yang M, Jiang J, Liu P, Yang J (2012) Circuit-switched on-chip photonic interconnection network. In: Proceedings of the 9th international conference on group IV photonics, pp 282–284Google Scholar
  23. 23.
    Adi CAD, Mtasutani H, Koibuchi M, Irie H, Miyoshi T, Yoshinaga T (2010) An efficient path setup for a photonic network-on-chip. In: Proceeding of the first international conference on networking and computing, pp 156–161Google Scholar
  24. 24.
    Chan J, Hendry G, Bergman K, Carloni L (2011) Physical-layer modeling and system-level design of chip-scale photonic interconnection networks. IEEE Trans Comput-Aided Des Integr Circuits Syst 30(10):1507–1520CrossRefGoogle Scholar
  25. 25.
    Matsutani H, Koibuchi M, Amano H, Yoshinaga T, Prediction router: yet another low latency on-chip router architecture. In: Proceedings of the 15th IEEE international symposium on high-performance computer architecture (HPCA 2009), pp 367–378Google Scholar
  26. 26.
    Ye Y, Xu J, Huang B, Wu X, Zhang W, Wang X, Nikdast M, Wang Z, Liu W, Wang Z (2013) 3-D mesh-based optical network-on-chip for multiprocessor system-on-chip. IEEE Trans Comput-Aided Des Integr Circuits Syst 32(4):584–596CrossRefGoogle Scholar
  27. 27.
    Wang J et al (2013) CPNoC: an energy-efficient photonic network-on-chip. In: Proceeding of the 27th international conference on advanced information networking and applications workshops (WAINA), pp 1571–1576Google Scholar
  28. 28.
    Shacham A et al (2008) Photonic networks-on-chip for future generations of chip multiprocessors. IEEE Trans Comput 57(9):1246–1260MathSciNetCrossRefGoogle Scholar
  29. 29.
    Petracca M, Lee B, Bergman K, Carloni L (2008) Design exploration of optical interconnection networks for chip multiprocessors. In: Proceeding of the 16th IEEE symposium high performance interconnects, pp 31–40Google Scholar
  30. 30.
    Vantrease D et al (2008) System implications of emerging nanophotonic technology. In: Proceeding of the 35th international symposium on computer architecture I (SCA’08), pp 153–164Google Scholar
  31. 31.
    Vantrease D, Binkert NL, Schreiber R, Lipasti MH (2009) Light speed arbitration and flow control for nanophotonic interconnects. In: Proceeding of the 42nd annual IEEE/ACM international symposium on microarchitecture (MICRO-42), pp 304–315Google Scholar
  32. 32.
    Gu H, Xu J, Zhang W (2009) A low-power fat tree-based optical network on-chip for multiprocessor system-on-chip. In: Design, automation and test in Europe (DATE), pp 3–8Google Scholar
  33. 33.
    Pasricha S, Dutt N (2008) ORB: an on-chip optical ring bus communication architecture for multi-processor systems-on-chip. In: Proceeding of Asia South Pacific conference design automation, pp 789–794Google Scholar
  34. 34.
    Beausoleil R et al (2008) A nanophotonic interconnect for high-performance many-core computation. In: Proceeding of the 16th IEEE symposium in high performance interconnects, pp 182–189Google Scholar
  35. 35.
    Zhang X, Louri A (2010) A multilayer nanophotonic interconnection network for on-chip many-core communications. In: Proceeding of the 47th ACM/IEEE design and automation conference (DAC), pp 156–161Google Scholar
  36. 36.
    Morris RW, Kodi AK, Louri A, Whaley RD (2014) Three-dimensional stacked nanophotonic network-on-chip architecture with minimal reconfiguration. IEEE Trans Comput 63(1):243–255MathSciNetCrossRefGoogle Scholar
  37. 37.
    Kirman K, Martinez J (2010) A power-efficient all-optical on-chip interconnect using wavelength-based oblivious routing. In: Proceeding of the 15th edition of ASPLOS on architectural support for programming languages and operating systems, pp 15–28Google Scholar
  38. 38.
    Aggarwal A, Bar-Noy A, Coppersmith D, Ramaswami R, Schieber B, Sudan M (1994) Efficient routing in optical networks. J ACM 43(6):973–1001MathSciNetCrossRefGoogle Scholar
  39. 39.
    Pan Y, Kim J, Memik G (2010) Flexishare: channel sharing for an energy-efficient nanophotonic crossbar. In: International symposium high-performance computer architecture (HPCA), pp 1–12Google Scholar
  40. 40.
    Wang H et al (2007) On the design of a \(4\times 4\) nonblocking nanophotonic switch for photonic networks on chip. In: Proceeding of frontiers in nanophotonics and plasmonicsGoogle Scholar
  41. 41.
    Hendry G, Robinson E, Gleyzer V, Chan J, Carloni L, Bliss, N, Bergman K (2010) Circuit-switched memory access in photonic interconnection networks for high-performance embedded computing. In: Proceeding of the international conference for high performance computing, networking, storage and analysis (SC), pp 1–12Google Scholar
  42. 42.
    Chan J, Bergman K (2012) Photonic interconnection network architectures using wavelength-selective spatial routing for chip-scale communications. IEEE/OSA J Opt Commun Netw 4(3):189–201CrossRefGoogle Scholar
  43. 43.
    Shacham A, Bergman K, Carloni L (2007) On the design of a photonic network-on-chip. In: Proceeding of the first international symposium on networks-on-chip (NoCs), pp 53–64Google Scholar
  44. 44.
    Hendry G et al (2011) Time-division-multiplexed arbitration in silicon nanophotonic networks-on-chip for high-performance chip multiprocessors. J Parallel Distrib Comput 71:641–650CrossRefGoogle Scholar
  45. 45.
    Hendry G et al (2010) Silicon nanophotonic network-on-chip using TDM arbitration. In: Proceeding of IEEE symposium on high-performance interconnects, pp 88–95Google Scholar
  46. 46.
    Pan Y, Kumar P, Kim J, Memik G, Zhang Y, Choudhary A (2009) Firefly: illuminating future network-on-chip with nanophotonics. Int Symp Comput Archit (ISCA), pp 429–440Google Scholar
  47. 47.
    Tan X, Yang M, Zhang L, Wang X, Jiang Y (2014) A hybrid optoelectronic networks-on-chip architecture. J Lightwave Technol 32(5):991–998CrossRefGoogle Scholar
  48. 48.
    Ben Ahmed A, Ben Abdallah A (2014) Graceful deadlock-free fault-tolerant routing algorithm for 3D network-on-chip architectures. J Parallel Distrib Comput 74–4:2229–2240CrossRefGoogle Scholar
  49. 49.
    Ben Ahmed A, Ben Abdallah A (2013) Architecture and design of high-throughput, low-latency, and fault-tolerant routing algorithm for 3D-network-on-chip (3D-NoC). J Supercomput 66–3:1507–1532CrossRefGoogle Scholar
  50. 50.
    Ye Y et al (2013) System-level analysis of mesh-based hybrid optical-electronic network-on-chip. In: IEEE international symposium on circuits and systems, pp 321–324Google Scholar
  51. 51.
    Preston K et al (2011) Performance guidelines for WDM interconnects based on silicon microring resonators. In: Conference on lasers and electro-optics (CLEO), pp 1–2Google Scholar
  52. 52.
    Brusberg L et al (2012) Single-mode glass waveguide platform for DWDM chip-to-chip interconnects. In: Proceeding of the 62nd conference on electronic components and technology, pp 1532–1539Google Scholar
  53. 53.
    Sun C et al (2012) DSENT-a tool connecting emerging photonics with electronics for opto-electronic networks-on-chip modeling. In: Proceeding of the sixth IEEE/ACM international symposium on networks-on-chip (NoCs), pp 201–210Google Scholar
  54. 54.
    Chan J, Hendry G, Biberman A, Bergman K, Carloni L (2010) PhoenixSim: a simulator for physical-layer analysis of chip-scale photonic interconnection networks. In: Design, automation and test in Europe (DATE), pp 691–696Google Scholar
  55. 55.
    Kahng A, Li B, Peh L-S, Samadi K (2012) Orion 2.0: a power-area simulator for interconnection networks. IEEE Trans Very Large Scale Integr (VLSI) Syst 20–1:191–196CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media New York 2015

Authors and Affiliations

  1. 1.Adaptive Systems Laboratory, Graduate School of Computer Science and EngineeringThe University of AizuAizu-WakamatsuJapan

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