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Improving fault-tolerance capability of on-chip binary CDMA bus

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Abstract

Shrinking technology and growing complexity of the contemporary system on chip designs require high performance and reliable interconnection architecture. Binary CDMA on-chip bus permits simultaneous use of the shared communication medium by multiple data streams and alleviates contention and queuing delays experienced by a conventional time-division multiplexing shared bus. In this paper, we present an encoding scheme for improving reliability of the on-chip interconnect system based on a binary CDMA bus. Without adding extra wires to the bus, the proposed encoding method replaces the standard binary encoding with a non-weighted code which tolerates single-bit error at any bus wire within the timing window of a single CDMA transaction. In addition, we derive constraints for a codeword selection under which the single-bit error tolerance is achieved and provide a recursive algorithm for code construction. Simulation results show that the proposed encoding scheme significantly improves the post-decoding bit error rate performance of the binary CDMA bus under a binary symmetric channel model.

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Acknowledgments

This work was supported by the Serbian Ministry of Education, Science and Technological Development, Project No. TR-32009—“Low-Power Reconfigurable Fault-Tolerant Platforms”.

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  1. Faculty of Electronic Engineering, University of Nis, A. Medvedeva 14, Nis, 18000, Serbia

    Tatjana R. Nikolic, Goran S. Nikolic, Goran Lj. Djordjevic & Mile K. Stojcev

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  1. Tatjana R. Nikolic
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  2. Goran S. Nikolic
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  3. Goran Lj. Djordjevic
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Correspondence to Tatjana R. Nikolic.

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Nikolic, T.R., Nikolic, G.S., Djordjevic, G.L. et al. Improving fault-tolerance capability of on-chip binary CDMA bus. J Supercomput 72, 275–294 (2016). https://doi.org/10.1007/s11227-015-1513-x

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  • DOI: https://doi.org/10.1007/s11227-015-1513-x

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