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Voltage scaling and dark silicon in symmetric multicore processors


As technology scales further, multicore and many-core processors emerge as an alternative to keep up with performance demands. However, because of power and thermal constraints, we are obliged to power off remarkable area of chip. Many innovative techniques have been presented to improve energy efficiency and maintain utilization at the highest level. In this paper, we discuss different models and methods of exploiting dark silicon, and by using dynamic voltage and frequency scaling in Amdahl’s law and considering memory overheads, we attempt to decrease amount of dark silicon and improve performance and performance per watt/joule. We propose high-performance and energy-efficient multicore architectures for variety of parallelisms and memory-intensities in workloads. According to the results, by voltage scaling, for a highly parallel CPU-intensive workload, we reach improvements of approximately \(5.2{\times }\) and \(3.78{\times }\) in performance per watt and performance per joule, respectively, while about 27 % reduction of performance should be tolerated. For memory-intensive applications, a negligible change in speedup is detected by scaling, while performance per watt and performance per joule for both serial and parallel applications lead to around \(6{\times }\) enhancements.

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  1. Moore G (1965) Moore’s law. Electronics Magazine

  2. Venkatesh G, Sampson J, Goulding N, Garcia S, Bryksin V, Lugo-Martinez J, Swanson S, Taylor MB (2010) Conservation cores. In: Proceedings of the fifteenth edition of ASPLOS on architectural support for programming languages and operating systems-ASPLOS ’10, vol 38, no 1, p 205

  3. Esmaeilzadeh H, Blem E, St.Amant R, Sankaralingam K, Burger D, St Amant R, Sankaralingam K, Burger D (2011) Dark silicon and the end of multicore scaling. In: 38th annual international aymposium on Computer architecture (ISCA), 2011, vol 32, no 3, pp 365–376

  4. ITRS (2010) International Technology Roadmap for Semiconductors. ITRS [Online]. Available

  5. Esmaeilzadeh H, Blem E, St Amant R, Sankaralingam K, Burger D (2013) Power challenges may end the multicore era. Commun ACM 56(2):93–102

    Article  Google Scholar 

  6. Hsu BC-H (2003) Compiler-directed dynamic voltage and frequency scaling for cpu power and energy reduction. Ph.D. Dissertion, State University of New Jersey, USA

  7. Swaminathan K, Kultursay E, Saripalli V, Narayanan V, Kandemir MT, Datta S (2013) Steep-slope devices: from dark to dim silicon. IEEE Micro 33(5):50–59

    Article  Google Scholar 

  8. Cho S, Melhem RG (2008) Corollaries to Amdahl’s law for energy. Comput Archit Lett 7(1):25–28

    Article  Google Scholar 

  9. Hill MD, Marty MR (2008) Amdahl’s law in the multicore era. IEEE Comput 41(7):33–38

    Article  Google Scholar 

  10. Eyerman S, Eeckhout L (2010) Modeling critical sections in Amdahl’s law and its implications for multicore design. ACM SIGARCH Comput Archit News 38(3):362

    Article  Google Scholar 

  11. Marowka A (2013) Analytical modeling of energy efficiency in heterogeneous processors. Comput Electr Eng 39(8):2566–2578

    Article  Google Scholar 

  12. Marowka A (2012) Extending Amdahl’s law for heterogeneous computing. In: Proceedings of the 2012 10th IEEE international symposium on parallel and distributed processing with applications, ISPA 2012, pp 309–316

  13. Sun X-H, Chen Y (2010) Reevaluating Amdahl’s law in the multicore era. J Parallel Distrib Comput 70(2):183–188

    MATH  Article  Google Scholar 

  14. Lee JLJ, Kim NSKNS (2009) Optimizing throughput of power- and thermal-constrained multicore processors using DVFS and per-core power-gating. In: 2009 46th ACM/IEEE Design Automation Conference, p 47

  15. Lee J, Kim NS (2012) Analyzing potential throughput improvement of power- and thermal-constrained multicore processors by exploiting DVFS and PCPG. IEEE Trans Very Large Scale Integr Syst 20(2):225–235

    Article  Google Scholar 

  16. Patki T, Lowenthal DK, Rountree B, Schulz M, de Supinski BR (2013) Exploring hardware overprovisioning in power-constrained, high performance computing. In: Proceedings of the 27th international ACM conference on international conference on supercomputing-ICS ’13, p 173

  17. Shafique M, Garg S, Henkel J, Marculescu D (2014) The EDA challenges in the dark silicon era. In: Proceedings of the 51st annual design automation conference-DAC ’14, pp 1–6

  18. Taylor MB (2013) A landscape of the new dark silicon design regime. IEEE Micro 33(5):8–19

    Article  Google Scholar 

  19. Gnad D, Shafique M, Kriebel F, Rehman S, Sun D, Henkel J (2015) Hayat: harnessing dark silicon and variability for aging deceleration and balancing. In: Proceedings of the 52nd annual design automation conference on-DAC ’15, pp 1–6

  20. Shafique M, Gnad D, Garg S, Henkel J (2015) Variability-aware dark silicon management in on-chip many-core systems. In: Proceedings of the 2015 design, automation and test in Europe conference and exhibition, no 2, pp 387–392

  21. Kriebel F, Rehman S, Sun D, Shafique M, Henkel J (2014) ASER: adaptive soft error resilience for reliability-heterogeneous processors in the dark silicon era. In: Proceedings of the 51st annual design automation conference, pp 12:1–12:6

  22. Raghavan A, Luo Y, Chandawalla A, Papaefthymiou M, Pipe KP, Wenisch TF, Martin MMK (2012) Computational sprinting. In: IEEE international symposium on high-performance comp architecture, pp 1–12

  23. Henkel J, Khdr H, Pagani S, Shafique M (2015) New trends in dark silicon. In: Proceedings of the 52nd annual design automation conference on-DAC ’15, pp 1–6

  24. Sohail HB, Thottethodi M (2011) Dark silicon is sub-optimal and avoidable. Technical Report, Purdue University

  25. Wang L, Skadron K (2013) Dark vs. dim silicon and near-threshold computing extended results. Technical Report UVA-CS-13-01, Department of Computer Science, University of Virginia

  26. Nejatollahi H, Salehi ME (2014) Effect of voltage scaling on symmetric multicore’s speed-up. In: 2014 22nd Iranian conference on electrical engineering (ICEE)

  27. Sakurai T, Newton AR (1990) Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas. IEEE J Solid-State Circuits 25(2), pp 584–594

  28. Shebaita A, Ismail Y (2008) Multiple threshold voltage design scheme for CMOS tapered buffers. IEEE Trans Circuits Syst II Express Briefs 55(1):21–25

    Article  Google Scholar 

  29. Weste NHE, Harris DM (2011) CMOS VLSI design: a circuits and systems perspective. Pearson Education, India

  30. Li NP, Sheng , Ahn J, Brockman, Jay B, Jouppi (2009) McPAT 1.0: an integrated power, area, and timing modeling framework for multicore architectures. HP Labs

  31. Borkar S (2007) Thousand core chips: a technology perspective. In: Proceedings of the 44th annual design automation conference, pp 746–749

  32. Chung ES, Milder PA, Hoe JC, Mai K (2010) Single-chip heterogeneous computing: does the future include custom logic, FPGAs, and GPGPUs? In: 2010 43rd annual IEEE/ACM international symposium on microarchitecture, pp 225–236

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This research was in part supported by a Grant from IPM (No. CS1394-4-14).

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Correspondence to Mostafa E. Salehi.

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Nejatollahi, H., Salehi, M.E. Voltage scaling and dark silicon in symmetric multicore processors. J Supercomput 71, 3958–3973 (2015).

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  • Dark silicon
  • Voltage and frequency scaling
  • Symmetric multicore
  • Amdahl’s law