Integrated circuit-packet switching NoC with efficient circuit setup mechanism

Abstract

Reducing the NoC power is critical for scaling up the number of nodes in future many-core systems. Most NoC designs adopt packet-switching to benefit from its high throughput and excellent scalability. These benefits, however, come at the price of the power consumption and latency overheads of routers. Circuit-switching, on the other hand, enjoys a significant reduction in power and latency of communication by directing data over pre-established circuits, but the relatively large circuit setup time and low resource utilization of this switching mechanism is often prohibitive. In this paper, we address one of the major problems of circuit-switching, i.e. the circuit setup time overhead, by an efficient and fast algorithm based on the time-division multiplexing scheme. We then further improve the performance by reserving circuits for anticipated messages, and hence completely hide circuit setup time. To address the low resource utilization problem, we integrate the proposed circuit-switching into a packet-switched NoC and use unused circuit resources to transfer packet-switched data. Evaluation results show considerable reduction in NoC power consumption and packet latency.

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Correspondence to Mehdi Modarressi.

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Pakdaman, F., Mazloumi, A. & Modarressi, M. Integrated circuit-packet switching NoC with efficient circuit setup mechanism. J Supercomput 71, 2787–2807 (2015). https://doi.org/10.1007/s11227-014-1337-0

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Keywords

  • Network-on-chip
  • Circuit-switching
  • Time-division multiplexing
  • Prediction