A methodology for speeding up edge and line detection algorithms focusing on memory architecture utilization

Abstract

In this paper, a new methodology for speeding up edge and line detection algorithms is presented, achieving improved performance over the state of the art software library OpenCV (speedup from 1.35 up to 2.22) and other conventional implementations, in both general and embedded processors, by reducing the number of load/store and arithmetic instructions, the number of data cache accesses and data cache misses in memory hierarchy and the algorithm memory size. This is achieved by fully exploiting the combination of the software and hardware parameters which are considered simultaneously as one problem and not separately. Furthermore, the edge and line detection algorithms have been simplified for a computer vision application in a Virtex-5 Xilinx FPGA using Microblaze soft processor (detection and measurement of flow fronts in a microfluid device); it achieves speedup up to 660 times in comparison with conventional software implementations.

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Acknowledgments

This research has been co-financed by the European Union (European Social Fund ESF) and Greek national funds through the Operational Program “Education and Lifelong Learning” of the National Strategic Reference Framework (NSRF)–Research Funding Program: Heracleitus II. Investing in knowledge society through the European Social Fund. The results were co-financed by Hellenic Funds and the European Regional Development Fund (ERDF) under ESPA 2007–2013 (MICRO2-SE-G). The machine vision algorithm and the SW model were introduced/patented by Micro2gen [72]. Part of this research has been supported by the Public Welfare Foundation ‘Propondis’ research funds.

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Correspondence to Vasilios Kelefouras.

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Kelefouras, V., Kritikakou, A. & Goutis, C. A methodology for speeding up edge and line detection algorithms focusing on memory architecture utilization. J Supercomput 68, 459–487 (2014). https://doi.org/10.1007/s11227-013-1049-x

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Keywords

  • Data reuse
  • Data cache
  • Assosiativity
  • FPGA
  • Memory management
  • Tiling
  • Canny
  • Hough