Skip to main content
SpringerLink
Log in

Dual-execution mode processor architecture

  • Published:
The Journal of Supercomputing Aims and scope Submit manuscript

Abstract

In this research work, we propose a novel embedded dual-execution mode 32-bit processor architecture (QSP32), which supports queue and stack programming models. The QSP32 core is based on a high performance produced order parallel queue architecture and is targeted for applications constrained in terms of area, memory, and power requirements. The design focuses on the ability to execute queue programs and also to support stack programs without a considerable increase in hardware to the base queue architecture. A prototype implementation of the processor is produced by synthesizing the high level model for a target FPGA device. We present the architecture description and design results in a fair amount of details. From the design and evaluation results, the QSP32 core efficiently executes both queue and stack based programs and achieves on average about 65 MHz speed. In addition, when compared to the base single-mode architecture (PQP), the QSP32 core requires only about 2.41% additional hardware. Moreover, the prototype fits on a single FPGA device, thereby eliminating the need to perform multi-chip partitioning which results in a loss of resource efficiency.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. De Micheli G, Ernst R, Wolf W (2001) Readings in hardware/software co-design. Kaufmann, Los Altos, ISBN 1-55860-702-1

    Google Scholar 

  2. Sowa M, Abderazek BA, Yoshinaga T (2005) Parallel queue processor architecture based on produced order computation model. Int J Supercomput 32(3):217–229

    Article  Google Scholar 

  3. Abderazek BA, Yoshinaga T, Sowa M (2006) High-level modeling and FPGA prototyping of produced order parallel queue processor core. Int J Supercomput 38(1):3–15

    Article  Google Scholar 

  4. P6 Power Data Slides provided by Intel Corp to Universities

  5. Bisshop B, Killiher T, Irwin M (1999) The design of register renaming unit. In: Proceedings of Great Lakes symposium on VLSI

  6. Akanda M, Abderazek BA, Kawata S, Sowa M (2005) An efficient dynamic Switching Mechanism (DSM) for Hybrid Processor Architecture. In: Proceedings of Springer’s lecture note in computer science, 6–9 December 2005. Lecture notes in computer science, vol 3824. Springer, Berlin, pp 77–86

    Google Scholar 

  7. Lewis D et al (2002) The stratix logic and routing architecture. In: FPGA-02, international conference on FPGA, pp 12–20

  8. Cadence Design Systems. http://www.cadence.com/

  9. Altera Design Software. http://www.altera.com/

  10. Abderazek BA, Arsenji M, Shigeta S, Yoshinaga T, Sowa M (2004) Queue processor for novel queue computing paradigm based on produced order scheme. In: Proceedings of HPC, IEEE CS, July 2004, pp 169–177

  11. Arahata F, Nishii O, Uchiyama K, Nakagawa N (1997) Functional verification of the superscalar SH-4 microprocessor. In: Proceedings of the international conference Compcon97, Feb 1997, pp 115–120

  12. SuperH RISC engine SH-1/Sh-2/Sh-DSP programming manual. http://www.renesas.com

  13. Maejima H, Kinaga M, Uchiyama K (1997) Design and architecture for low power/high speed RISC microprocesor: SuperH. IEICE Trans Electron E 80(12):1539–1549

    Google Scholar 

  14. Takahashi H, Abiko S, Mizushima S (1997) A 100 MIPS high speed and low power digital signal processor. IEICE Trans Electron E 80(12):1546–1552

    Google Scholar 

  15. Lysecky R, Vahid F (2005) A study of the speedups and competitiveness of FPGA soft processor cores using dynamic hardware/software partitioning. In: Proceedings of design automation and test in Europe (DATE’05), vol. 1, Munich, Germany, March 2005, pp 18–23

  16. Abderazek BA (2002) Dynamic instructions issue algorithm and a queue execution model toward the design of hybrid processor architecture. PhD thesis, Graduate School of Information Systems, the University of Electro-Communications, March 2002

  17. Koopman JP. Stack computer. Ellis Horwood Limited

  18. Sheliga M, Sha EH (1996) Hardware/software co-design with the HMS framework. J VLSI Signal Process Syst 13(1):37–56

    Article  Google Scholar 

  19. Kim K, Kim HY, Kim TG (2003) Top-down retargetable framework with token-level design for accelerating simulation time of processor architecture. IEICE Trans Fundam Electron Commun Comput Sci E 86-A(12):3089–3098

    Google Scholar 

  20. Smith JE, Sohi G (1995) The microarchitecture of superscalar processors. Proc IEEE 83(12):1609–1624

    Article  Google Scholar 

  21. McGhan H, O’Connor M (1998) PicoJava: a direct execution engine for Java bytecode. Comput Trans 31(10):22–30

    Google Scholar 

  22. Advanced RISC Machines Ltd (1994) ARM7DMI Data Sheet

  23. Advanced RISC Machines Ltd (2001) ARM Architecture Reference Manual. 02 September 2001

  24. Gaisler Research Laboratory (2004) LEON2 XST User’s Manual 1.0.22 edition, May 2004

  25. Preiss BR, Hamacher VC (1985) Data flow on queue machine. In: ISCA 1985, 12th international symposium on computer architecture, Boston, August 1985, pp 342–351

  26. Advancel Logic Corporation. Tiny2J microprocessor core for Javacard applications. http://www.advancel.com

  27. http://ultratechnology.com/

  28. Gowan M, Biro L, Jackson D (1998) Power considerations in the design of the alpha 21264 microprocessor. In: CAD1998, the 35th design automation conference, June 1998, pp 726–731

  29. Tiwari V et al (1998) Reducing power in high-performance microprocessors. In: CAD 1998, 35th design automation conference, San Francisco, June 1998, pp 732–737

  30. Fernandes M, Llosa J, Topham N (1997) Using queues for register file organization in VLIW. Technical Report ECS-CSG-29-97, University of Edinburgh, Department of Computer Science

  31. Heath LS, Pemmaraju SV, Trenk AN (1996) Stack and queue layouts of directed acyclic graphs: part I. SIAM J Comput 23(4):1510–1539

    MathSciNet  Google Scholar 

  32. Schmit H, Levine B, Ylvisaker B (2002) Queue machines: hardware compilation in hardware. In: FCCM’02, 10th annual IEEE symposium on field-programmable custom computing machines, pp 152–161

  33. Canedo A, Abderazek BA, Sowa M (2006) Code generation algorithms for consumed and produced order queue machines. Master thesis, Graduate School of Information Systems, University of Electro-Communications, September 2006

  34. Merrill J (2003) GENERIC and GIMPLE: a new tree representation for entire functions. In: Proceedings of GCC Developers Summit, pp 171–180

  35. VijayKrishnan N (1998) Issues in the design of JAVA processor architecture. PhD thesis, University of South Florida, Tampa, FL-33620, December 1998

  36. Mattson D, Christensson M (2004) Evaluation of synthesizable CPU cores. Master’s thesis, Department of Computer Engineering, Chalmers University of Technology

  37. 2006 EDN DSP directory. http://www.edn.com/dspdirectory

  38. CPU86 8088/8086 FPGA IP Core. http://www.ht-lab.com/

Download references

Author information

Authors and Affiliations

  1. Network Computing Laboratory, Graduate School of Information Systems, National University of Electro-Communications, 1-5-1 Chofu-gaoka, Chofu-shi, Tokyo, 1828585, Japan

    Md. Musfiquzzaman Akanda, Ben A. Abderazek & Masahiro Sowa

Authors
  1. Md. Musfiquzzaman Akanda
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Ben A. Abderazek
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Masahiro Sowa
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Md. Musfiquzzaman Akanda.

Additional information

The QSP32 research work is partially supported by the Graduate School of Information Systems at the National University of Electro-Communications, Tokyo.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Akanda, M.M., Abderazek, B.A. & Sowa, M. Dual-execution mode processor architecture. J Supercomput 44, 103–125 (2008). https://doi.org/10.1007/s11227-007-0151-3

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11227-007-0151-3

Keywords

Search

Navigation