Implementation of the SHA-2 Hash Family Standard Using FPGAs

Abstract

The continued growth of both wired and wireless communications has triggered the revolution for the generation of new cryptographic algorithms. SHA-2 hash family is a new standard in the widely used hash functions category. An architecture and the VLSI implementation of this standard are proposed in this work. The proposed architecture supports a multi-mode operation in the sense that it performs all the three hash functions (256, 384 and 512) of the SHA-2 standard. The proposed system is compared with the implementation of each hash function in a separate FPGA device. Comparing with previous designs, the introduced system can work in higher operation frequency and needs less silicon area resources. The achieved performance in the term of throughput of the proposed system/architecture is much higher (in a range from 277 to 417%) than the other hardware implementations. The introduced architecture also performs much better than the implementations of the existing standard SHA-1, and also offers a higher security level strength. The proposed system could be used for the implementation of integrity units, and in many other sensitive cryptographic applications, such as, digital signatures, message authentication codes and random number generators.

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Correspondence to N. Sklavos.

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Sklavos, N., Koufopavlou, O. Implementation of the SHA-2 Hash Family Standard Using FPGAs. J Supercomput 31, 227–248 (2005). https://doi.org/10.1007/s11227-005-0086-5

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  • hash function standard
  • security
  • cryptography
  • hardware implementation
  • SHA-2 standard
  • AES standard