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T-count optimized quantum circuit for floating point addition and multiplication

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Abstract

Quantum computers perform computations using quantum-mechanical phenomena such as superposition and entanglement. Floating-point operations are employed in almost all conventional digital signal processors which evinces that floating-point numbers can be a viable candidate to be deployed with quantum information processing systems. In this paper, a T-count and T-depth optimized quantum floating-point addition and multiplication circuit are proposed. This work centers around improving the current structures of multi-qubit magnitude comparator, subtractor, leading zero detector, and reduces T-count and T-depth use by huge sum when contrasted with the existing works. The whole architecture of the quantum floating-point adder and multiplier is constructed using the aforementioned primary structures. The proposed quantum floating-point adder offers a T-count savings of 92.79\(\%\) over the existing work and T-depth improvement over 49.03 \(\%\) and 85.69 \(\%\) over the existing works by Nguyen and Van Meter (A space-efficient design for reversible floating point adder in quantum computing. arXiv:1306.3760) and Haener et al. (in: International conference on reversible computation, Springer, pp 162–174, 2018) respectively. The proposed structure shows an improvement of 82.74 \(\%\) and 71.58 \(\%\) in circuit size KQ reported in Nguyen and Van Meter and Haener et al. (2018) respectively despite quite larger ancilla than the hand-optimized circuit by Haener et al. (2018). The T-count and T-depth improvement of the proposed floating-point multiplier is around 93.87\(\%\) and circuit size KQ improvement is around 78.49\(\%\) than the existing quantum floating point circuit.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, College of Engineering and Technology, Faculty of Engineering and Technology, SRM Institute of Science and Technology, SRM Nagar, Kattankulathur, Kanchipuram, Chennai, TN, 603203, India

    S. S. Gayathri, R. Kumar & Samiappan Dhanalakshmi

  2. Indian Institute of Technology, Roorkee, India

    Brajesh Kumar Kaushik

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Gayathri, S.S., Kumar, R., Dhanalakshmi, S. et al. T-count optimized quantum circuit for floating point addition and multiplication. Quantum Inf Process 20, 378 (2021). https://doi.org/10.1007/s11128-021-03296-6

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