A new sign detection design for the residue number system based on quantum-dot cellular automata

Abstract

Sign detection has a wide application in digital fixed-point signal processing; however, it seems hard to conduct it in residue number systems (RNSs) based on complementary metal oxide semiconductor (CMOS). Also, quantum-dot cellular automata (QCA), as a useful substitution for CMOS technologies, provide many benefits such as low energy utilization and high velocity. However, up to now, there is not any paper that investigated the design of the QCA-based sign detection system. Therefore, here, we will introduce a method for RNS sign detection in the three-moduli set {2n+1 − 1, 2n − 1, 2n}. In the suggested design, we offer a new QCA-based design in one layer for sign detection of three-moduli set {2n+1 − 1, 2n − 1, 2n}. It is not only used for arithmetic units of RNS but also applied for cost and performance improvement of the total system. We simulate and analyze the proposed detection method using the QCADesigner simulator. We also compare the cell count, delay, and occupied area. Experimental results showed that the proposed architecture requires 5.60 µm2 of the circuit area, and the delay is decreased.

This is a preview of subscription content, access via your institution.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13

References

  1. 1.

    Bajard, J.-C., Imbert, L.: A full RNS implementation of RSA. Comput. IEEE Trans. 53(6), 769–774 (2004)

    Article  Google Scholar 

  2. 2.

    Konstantinides, K., Bhaskaran, V.: Monolithic architectures for image processing and compression. IEEE Comput. Graph. Appl. 6, 75–86 (1992)

    Article  Google Scholar 

  3. 3.

    Raghu, J., Ashok, B.: An Efficient Fast Sign Detection Algorithm for the RNS Moduli Set, 5(42), 8786–8788 (2016)

  4. 4.

    Szabo, N., Tanaka, R.: Residue arithmetic and its applications to computer technology. (1967) ed: McGraw-Hill, New York

  5. 5.

    Priyanka, G. S., Kumar, K. P.: Implementation of a fast sign detection algorithm for the RNS moduli set

  6. 6.

    Wade, J.: Including all learners: QCA’s approach. Br. J. Special Educ. 26(2), 80–82 (1999)

    Article  Google Scholar 

  7. 7.

    Pudi, V., Sridharan, K.: Low complexity design of ripple carry and Brent-Kung adders in QCA. Nanotechnol. IEEE Trans. 11(1), 105–119 (2012)

    Article  Google Scholar 

  8. 8.

    Walus, K., Budiman, R.A., Jullien, G.: Split current quantum-dot cellular automata-modeling and simulation. Nanotechnology, IEEE Transactions on 3(2), 249–255 (2004)

    Article  Google Scholar 

  9. 9.

    Norouzi, A., Heikalabad, S.R.: Design of reversible parity generator and checker for the implementation of nano-communication systems in quantum-dot cellular automata. Photon. Netw. Commun. 38(2), 231–243 (2019)

    Article  Google Scholar 

  10. 10.

    Bernstein, G.H., et al.: Magnetic QCA systems. Microelectron. J. 36(7), 619–624 (2005)

    Article  Google Scholar 

  11. 11.

    Sridharan, K., Pudi, V.: Design of basic digital circuits in QCA, in design of arithmetic circuits in quantum dot cellular automata nanotechnology: Springer, (2015) pp. 19–26

  12. 12.

    Walus, K., Jullien, G., Dimitrov, V.:Computer arithmetic structures for quantum cellular automata, in signals, systems and computers, 2004. Conference record of the thirty-seventh asilomar conference on, (2003) vol. 2, pp. 1435–1439: IEEE.

  13. 13.

    Henderson, S.C., Johnson, E.W., Janulis, J.R., Tougaw, P.D.: Incorporating standard CMOS design process methodologies into the QCA logic design process. Nanotechnol. IEEE Trans. 3(1), 2–9 (2004)

    Article  Google Scholar 

  14. 14.

    Das, J.C., De, D.: Reversible binary subtractor design using quantum dot-cellular automata. Front. Inform. Technol. Electron. Eng. 18(9), 1416–1429 (2017)

    Article  Google Scholar 

  15. 15.

    Abedi, D., Jaberipur, G., Sangsefidi, M.: Coplanar full adder in quantum-dot cellular automata via clock-zone-based crossover. Nanotechnol. IEEE Trans. 14(3), 497–504 (2015)

    Article  Google Scholar 

  16. 16.

    H. Aiken and W. Semon, "Advanced digital computer logic," Comput. Lab., Harvard Univ., Cambridge, Mass., Rep. WADC TR-59–472, 1959.

  17. 17.

    Flores, I.: The logic of computer arithmetic, Prentice-Hall, Inc., (1963)

  18. 18.

    Garner, H.L.: The residue number system. Electron. Comput. IRE Trans. 2, 140–147 (1959)

    Article  Google Scholar 

  19. 19.

    A. Svoboda and M. Valach, "Computer Progress in Czechoslovakia II, The Numerical Systems of Residue Classes," in Digital Information Processor: Wiley, 1962.

  20. 20.

    Molahosseini, A.S., Navi, K., Dadkhah, C., Kavehei, O., Timarchi, S.: Efficient reverse converter designs for the new 4-moduli sets and based on new CRTs. Circuits Syst. I Regul. Pap. IEEE Trans. 57(4), 823–835 (2010)

    MathSciNet  Article  Google Scholar 

  21. 21.

    Wang, W., Swamy, M., Ahmad, M. O.: RNS application for digital image processing, in system-on-chip for real-time applications, 2004. Proceedings. 4th IEEE international workshop on, (2004), pp. 77–80: IEEE

  22. 22.

    Radhakrishnan, D., Preethy, A.: A 32 Bit multiplier architecture using Galois fields (1998), The 2nd European Parallel and Distributed Syst. Conf., Vienna, Austria, July 1998

  23. 23.

    Hariri, A., Navi, K., Rastegar, R.: A simplified modulo (2 n-1) squaring scheme for residue number system, in computer as a tool, 2005. Eurocon 2005. The international conference on, 2005, vol. 1, pp. 615–618: IEEE

  24. 24.

    Szabo, N.: Sign detection in nonredundant residue systems. IEEE Trans. on Electron. Comput. 4(EC-11), 494–500 (1962)

    MathSciNet  Article  Google Scholar 

  25. 25.

    Al-Radadi, E., Siy, P.: RNS sign detector based on Chinese remainder theorem II (CRT II). Comput. Math. Appl. 46(10), 1559–1570 (2003)

    MathSciNet  Article  Google Scholar 

  26. 26.

    Akkal, M., Siy, P.: Optimum RNS sign detection algorithm using MRC-II with special moduli set. J. Syst. Architect. 54(10), 911–918 (2008)

    Article  Google Scholar 

  27. 27.

    Tomczak, T.: Fast sign detection for RNS. Circuits Syst. I Regul. Pap. IEEE Trans. 55(6), 1502–1511 (2008)

    MathSciNet  Article  Google Scholar 

  28. 28.

    Mohan, P.V.A.: RNS-to-binary converter for a new three-moduli set {2 n+ 1–1, 2 n, 2 n− 1}. Circuits Syst. Exp. Briefs IEEE Trans. on 54(9), 775–779 (2007)

    MathSciNet  Article  Google Scholar 

  29. 29.

    Dajani, O.: Emerging design methodology and its implementation through RNS and QCA. Electrical Engineering, Wayne State University, Detroit, Michigan, PhD (2013)

    Google Scholar 

  30. 30.

    Molahosseini, A. S., Sorouri, S., Zarandi, A. A. E.: Research challenges in next-generation residue number system architectures, in 2012 7th international conference on computer science & education (ICCSE), pp. 1658–1661 (2012) IEEE

  31. 31.

    Das, J.C., De, D., Mondal, S.P., Ahmadian, A., Ghaemi, F., Senu, N.: QCA based error detection circuit for nano communication network. IEEE Access 7, 67355–67366 (2019)

    Article  Google Scholar 

  32. 32.

    Kazemifard, N., Navi, K.: Implementing RNS arithmetic unit through single electron quantum-dot cellular automata. Int. J. Comput. Appl. 163(4), 20 (2017)

    Google Scholar 

  33. 33.

    Xu, M., Bian, Z., Yao, R.: Fast sign detection algorithm for the RNS moduli set. Very Large Scale Integr. (VLSI) Syst. IEEE Trans. 23(2), 379–383 (2015)

    Article  Google Scholar 

  34. 34.

    Piestrak, S.J.: Design of residue generators and multioperand modular adders using carry-save adders. IEEE Trans. Comput. 43(1), 68–77 (1994)

    Article  Google Scholar 

  35. 35.

    Zimmermann, R.: Efficient VLSI implementation of modulo (2 n±1) addition and multiplication, in Computer arithmetic, 1999. Proceedings. 14th IEEE symposium on, pp. 158–167 (1999), IEEE

  36. 36.

    Furuya, K.: Design methodologies of comparators based on parallel hardware algorithms, in 2010 10th international symposium on communications and information technologies, (2010)

  37. 37.

    Ulman, Z.D.: Sign detection and implicit-explicit conversion of numbers in residue arithmetic. IEEE Trans. Comput. 6, 590–594 (1983)

    Article  Google Scholar 

  38. 38.

    Van Vu, T.: Efficient implementations of the Chinese remainder theorem for sign detection and residue decoding. Comput. IEEE Trans. 100(7), 646–651 (1985)

    MATH  Google Scholar 

Download references

Acknowledgements

This project was funded by National Key R&D Program of China (No. 2017YFB0503604; No. 2017YFB0503801), Electronic Fence System Project, China Postdoctoral Science Foundation, the Project of FDCT, and the Project of Macao Foundation.

Author information

Affiliations

Authors

Corresponding author

Correspondence to Daming Li.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and Permissions

About this article

Verify currency and authenticity via CrossMark

Cite this article

Deng, L., Liu, W., Li, D. et al. A new sign detection design for the residue number system based on quantum-dot cellular automata. Photon Netw Commun (2021). https://doi.org/10.1007/s11107-021-00941-z

Download citation

Keywords

  • Sign detection
  • Quantum-dot cellular automata (QCA)
  • Residue number system (RNS)
  • Concurrent arithmetic applications