Design of reversible parity generator and checker for the implementation of nano-communication systems in quantum-dot cellular automata
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Complementary metal-oxide semiconductor (CMOS) technology may face so much problems in future due to the smaller size of transistors and increase in circuits’ volume and chips temperature. A new technology that can be a good alternative to CMOS circuits is quantum-dot cellular automata (QCA). These technologies have features such as a very low power consumption, high speed and small dimensions. In nano-communication system, error detection and correction in a receiver message are major factors. In addition, circuit reversibility in QCA helps designs a lot. In this research, generator and checker circuit of the reversible parity and eventually their nano-communication system are designed reversible using odd parity bit. The proposed circuits and the theoretical values are tested by QCADesigner 2.0.3 simulator to show the correct operation of the circuits. According to the simulation results, the proposed circuits compared with the previous structure improve delay by 90–75–35% in generator and checker structures of parity and their reversibility of nano-communication system, respectively. The proposed circuits are used in nano-transmitters and nano-receivers.
KeywordsNano-communication system Quantum-dot cellular automata Parity generator Parity checker Reversible
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