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70-Gb/s amplitude-shift-keyed system with 10-GHz clock recovery circuit using duty cycle division multiplexing

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Abstract

The performance of ASK over DCDM for up to seven channels is reported. The aggregate bit rate of 70 Gb/s is achieved with only 160-GHz modulation bandwidth. The clock and data recovery are realized at 10-GHz clock rate, which is very economic and efficient. At 7 × 10 Gb/s, the worst receiver sensitivity of −10 dBm, OSNR of 41.5 dB and chromatic dispersion tolerance of ±7 ps/nm are achieved. Whereas, for the best channel, the receiver sensitivity, OSNR, and chromatic dispersion tolerance are −23.5 dBm, 29 dB, and ±36 ps/nm, respectively.

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Authors and Affiliations

  1. Department of Computer and Communication Systems Engineering, University Putra Malaysia, 43400, Serdang, Malaysia

    Ghafour Amouzad Mahdiraji, Makhfudzah Mokhtar, Amin Malek Mohammadi, Ahmad Fauzi Abas, Safuraa Mohd Basir & Raja Syamsul Azmir Raja Abdullah

  2. Significant Technologies Sdn. Bhd., 43400, Serdang, Selangor, Malaysia

    Mohamad Khazani Abdullah

Authors
  1. Ghafour Amouzad Mahdiraji
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  2. Mohamad Khazani Abdullah
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  3. Makhfudzah Mokhtar
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  4. Amin Malek Mohammadi
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  5. Ahmad Fauzi Abas
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  6. Safuraa Mohd Basir
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  7. Raja Syamsul Azmir Raja Abdullah
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Correspondence to Ghafour Amouzad Mahdiraji.

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Amouzad Mahdiraji, G., Abdullah, M.K., Mokhtar, M. et al. 70-Gb/s amplitude-shift-keyed system with 10-GHz clock recovery circuit using duty cycle division multiplexing. Photon Netw Commun 19, 233–239 (2010). https://doi.org/10.1007/s11107-009-0228-4

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  • DOI: https://doi.org/10.1007/s11107-009-0228-4

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