Abstract
In Intel’s “Tick-Tock” roadmap a new processor is first manufactured in the most advanced stable process technology, followed in a 1-year delay by introducing chips comprising same microarchitecture but manufactured in a newer scaled process technology. Tick-Tock is enabled by the automation of chip’s layout migration from an older into a newer process technology, known as hard-IP reuse. This is a very challenging computational task, involving billions of polygons. Migration algorithms have been thoroughly studied and implemented in the past but their computational capabilities fall short compared to today’s demand. We describe a hierarchy-driven computationally efficient algorithm for cell-based layout conversion, used by Intel in its Tick-Tock roadmap. The algorithm transforms the full chip conversion problem into successive problems of significantly smaller size, having feasible solutions if and only if the full chip problem does. The proposed algorithm preserves the design intent, its uniformity, portability and maintainability, a key for the success of large-scale projects.
Similar content being viewed by others
References
Burns JL, Feldman JA (1998) C5M—a control-logic layout synthesis system for high-performance microprocessors. IEEE Trans CAD Integr Circuits Syst 17(1):14–23
Burns JL, Newton AR (1987) Efficient constraint generation for hierarchical compaction. In: IEEE international conference on computer design, pp. 197–200
Chiang S-Y (2001) Foundries and the dawn of an open IP era. Computer 34(4):43–46
Fang F, Zhu J (2004) Automatic process migration of data-path hard IP libraries. In: Proceedings of the 2004 Asia and South Pacific design automation conference. IEEE Press, pp. 887–892
Intel’s Tick-Tock Model, http://www.intel.com/technology/tick-tock/index.htm
Klau G, Mutzel P (1999) Optimal compaction of orthogonal grid drawings. Lecture notes in computer science: integer programming and combinatorial optimization, vol 1610. Springer, Berlin, pp 304–319
Lengauer T (1984) On the solution of inequality systems relevant to IC-layout. J Algorithms 5(3):408–421
Lengauer T (1990) Compaction. In: Combinatorial algorithms for integrated circuit layout. Wiley, Chichester, pp 579–643
Moiseev K, Kolodny A, Wimer S (2009) Power-delay optimization in VLSI microprocessors by wire spacing. ACM Trans Des Autom Electron Syst 14(4):1–28 Article No. 55
Moiseev K, Kolodny A, Wimer S (2010) Interconnect bundle sizing under discrete design rules. IEEE Trans CAD Integr Circuits Syst 29(10):1650–1654
Nitzan R, Wimer S (2002) AMPS and SiClone integration for implementing 0.18 um to 0.13 um design migration. In: Proceedings of the Synoposys Users Group (SNUG) Conference, San Jose CA, March 2002
Patrignani M (2001) On the complexity of orthogonal compaction. Comput Geom 19(1):47–67
Perry TS (2008) Gordon Moore’s next act. IEEE Spectr 45(5):38–47
Reinhardt M (2002) Automatic layout modification: including design reuse of the alpha cpu in 0.13 micron soi technology. Kluwer, Norwell, MA, USA
Saleh R et al (2006) System-on-chip: reuse and integration. Proc IEEE 94(6):1050–1069
Sastry S, Parker A (1982) The complexity of two dimensional compaction of VLSI layouts. In: Proceedings of international conference on circuits and computers, pp 402–406
Schlag M, Liao YZ, Wong CK (1983) An algorithm for optimal two-dimensional compaction of VLSI layouts. Integration 1(2–3):179–209
Shaphir E, Pinter RY, Wimer S (2013) Cell-based interconnect migration by hierarchical optimization. Integration. doi:10.1016/j.vlsi.2013.10.003
Shin H, Sangiovanni-Vincentelli AL, Siquin CH (1986) Two-dimensional compaction by zone refining. In: Proceeding of the 23rd ACM/IEEE design automation conference, pp 115–122
Simultaneous, n-level hierarchical layout compaction, process migration and physical optimization. http://www.sagantec.com/SiClone.pdf
Wang L-Y, Lai Y-T (2001) Graph-theory-based simplex algorithm for VLSI layout spacing problems with multiple variables constraints. IEEE Trans CAD Integr Circuits Syst 20(8):967–979
Weste N, Harris D (2005) CMOS VLSI design: a circuits and systems perspective. Pearson, Addison-Wesley
Wimer S (2014) Planar CMOS to multi-gate layout conversion for maximal fin utilization. Integration 47:115–122
Yao S-Z, Cheng C-K, Dutt D, Nahar S, Lo C-Y (1993) Cell-based hierarchical pitchmatching compaction using minimal LP. In: Proceedings of the 30th international design automation conference, ACM, pp 395–400
Acknowledgments
The authors are thankful to Intel Corporation for supporting this work. They are also thankful for the useful reviewers’ comments, which helped improving the manuscript.
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Shaphir, E., Pinter, R.Y. & Wimer, S. Efficient cell-based migration of VLSI layout. Optim Eng 16, 203–223 (2015). https://doi.org/10.1007/s11081-014-9257-7
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s11081-014-9257-7