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Design method for unbalanced ternary logic family based on binary memristors

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Abstract

This paper proposes a design method for unbalanced ternary logic family based on hybrid design of binary memristors and CMOS transistors, building on the foundational positive ternary logic circuits. By using the symmetry of negative and positive ternary logics, negative ternary TAND, TOR, TI, 1-3 decoder and 2-9 decoder are derived from the previously designed positive ternary basic logic gate circuits. Furthermore, negative ternary XOR, XNOR, 3-1 encoder and 9-2 encoder are design-improved. For the first time, unbalanced ternary priority encoders are proposed, including a 3-1 priority encoder and a 9-2 priority encoder, of which the former is implemented with only seven memristors. The functionalities of these circuits are demonstrated through LTSpice simulations. Finally, hardware experiments were performed on a stable 20 \(\times \) 20 ZnO-based resistive switch array. Subsequent design of more complex digital logic circuits can benefit from this work.

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Data availability

The datasets generated and analyzed during the current study are available from the corresponding author on reasonable request.

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Acknowledgements

This work was supported in part by the National Natural Science Foundation of China under Grant 61871429, in part by the Natural Science Foundation of Zhejiang Province under Grant LY18F010012.

Funding

This work was funded by the National Natural Science Foundation of China (Grant No. 61871429), Natural Science Foundation of Zhejiang Province (Grant No. LY18F010012).

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Authors and Affiliations

  1. School of Electronics and Information, Hangzhou Dianzi University, Hangzhou, 310018, China

    Xiaoyuan Wang, Yingfei Sun, Jiawei Zhou & Xinhui Chen

  2. Department of Electrical and Computer Engineering, University of California, Santa Cruz, CA, 95064, USA

    Sung-Mo Kang

  3. School of Electrical and Electronic Engineering, The University of Western Australia, Crawley, WA, 6009, Australia

    Herbert Ho-Ching Iu

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  1. Xiaoyuan Wang
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  2. Yingfei Sun
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Correspondence to Xiaoyuan Wang.

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Wang, X., Sun, Y., Zhou, J. et al. Design method for unbalanced ternary logic family based on binary memristors. Nonlinear Dyn 112, 7615–7629 (2024). https://doi.org/10.1007/s11071-024-09402-4

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