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A general discrete memristor emulator based on Taylor expansion for the reconfigurable FPGA implementation and its application

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Abstract

The research on the memristor model and its high-precision hardware circuit experimental platform has gained significant attention. This paper presents a general discrete memristor emulator (GDME) and investigates its typical dynamic properties and operating frequency theoretically. To overcome the limitations of noise and bandwidth of commercial components on pinched hysteresis loops (PHLs), an operating frequency shifting method is proposed. An FPGA-based GDME hardware experiment platform is integrated into an acquisition card, enabling the digital domain processing of signals at the memristor’s two ports and showing the PHLs. The proposed method achieves an experimental maximum operating frequency (EMOF) of 20 GHz, approximately 3.3e3 times better than the existing method. Subsequently, the EMOF and PHLs of existing memristor models are expanded using a tenth-order GDME. Experimental results demonstrate that the proposed method exhibits high accuracy, reconfigurability, and speed. Finally, a 2D memristor logistic map of a coupled third-order GDME is designed, and the performance analysis reveals that the coupled memristor can further improve its stochastic performance.

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Acknowledgements

This work was supported in part by the National Natural Science Foundation of China (Grant No. U2030205, U2230206).

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Correspondence to Jia Zhao.

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Xu, B., Zou, S., Bai, L. et al. A general discrete memristor emulator based on Taylor expansion for the reconfigurable FPGA implementation and its application. Nonlinear Dyn 112, 1395–1414 (2024). https://doi.org/10.1007/s11071-023-09092-4

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